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20Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYu-Chee Tseng, Chin-Hao Wu, Fang-Jing Wu, Chi-Fu Huang, Chung-Ta King, Chun-Yu Lin, Jang-Ping Sheu, Chun-Yu Chen, Chi-Yuan Lo, Chien-Wen Yang, Chi-Wen Deng: A Wireless Human Motion Capturing System for Home Rehabilitation. Mobile Data Management 2009: 359-360
1995
19Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAnoop Singhal, Chi-Yuan Lo: Object oriented data modeling for VLSI/CAD. VLSI Design 1995: 25-29
18Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSo-Zen Yao, Chung-Kuan Cheng, Debaprosad Dutt, Surendra Nahar, Chi-Yuan Lo: A cell-based hierarchical pitchmatching compaction using minimal LP. IEEE Trans. on CAD of Integrated Circuits and Systems 14(4): 523-526 (1995)
1994
17no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLChi-Yuan Lo, Jirí Matousek, William L. Steiger: Algorithms for Ham-Sandwich Cuts. Discrete & Computational Geometry 11: 433-452 (1994)
16Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLShun-Lin Su, Charles H. Barry, Chi-Yuan Lo: A space-efficient short-finding algorithm [VLSI layouts]. IEEE Trans. on CAD of Integrated Circuits and Systems 13(8): 1065-1068 (1994)
1993
15Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSo-Zen Yao, Chung-Kuan Cheng, Debaprosad Dutt, Surendra Nahar, Chi-Yuan Lo: Cell-Based Hierarchical Pitchmatching Compaction Using Minimal LP. DAC 1993: 395-400
14Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAnoop Singhal, Robert M. Arlein, Chi-Yuan Lo: DDB: An Object Oriented Design Data Manager for VLSI CAD. SIGMOD Conference 1993: 467-470
13Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLNishit P. Parikh, Chi-Yuan Lo, Anoop Singhal, Kwok W. Wu: HS: a hierarchical search package for CAD data. IEEE Trans. on CAD of Integrated Circuits and Systems 12(1): 1-5 (1993)
1992
12no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLChi-Yuan Lo, Jirí Matousek, William L. Steiger: Ham-Sandwich Cuts in R^d STOC 1992: 539-545
11Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLCharles R. Bonapace, Chi-Yuan Lo: An O(n log m) algorithm for VLSI design rule checking. IEEE Trans. on CAD of Integrated Circuits and Systems 11(6): 753-758 (1992)
1991
10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLDebaprosad Dutt, Chi-Yuan Lo: On Minimal Closure Constraint Generation for Symbolic Cell Assembly. DAC 1991: 736-739
1990
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLChi-Yuan Lo, Ravi Varadarajan: An O(n1.5logn) 1-d Compaction Algorithm. DAC 1990: 382-387
8no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLNishit P. Parikh, Chi-Yuan Lo, Anoop Singhal, Kwok W. Wu: HS: A Hierarchical Search Package for CAD Data. ICCAD 1990: 478-481
1989
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLChong-Leong Ong, Jeong-Tyng Li, Chi-Yuan Lo: GENAC: An Automatic Cell Synthesis Tool. DAC 1989: 239-244
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLH. Shin, Chi-Yuan Lo: An Efficient Two-Dimensional Layout Compaction Algorithm. DAC 1989: 290-295
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLChi-Yuan Lo: Automatic Tub Region Generation for Symbolic Layout Compaction. DAC 1989: 302-306
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLCharles R. Bonapace, Chi-Yuan Lo: An O(nlogm) Algorithm for VLSI Design Rule Checking. DAC 1989: 503-507
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKuang-Wei Chiang, Surendra Nahar, Chi-Yuan Lo: Time-efficient VLSI artwork analysis algorithms in GOALIE2. IEEE Trans. on CAD of Integrated Circuits and Systems 8(6): 640-648 (1989)
1988
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKuang-Wei Chiang, Surendra Nahar, Chi-Yuan Lo: Time Efficient VLSI Artwork Analysis Algorithms in GOALIE2. DAC 1988: 471-475
1987
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLChi-Yuan Lo, Hao N. Nham, Ajoy K. Bose: Algorithms for an Advanced Fault Simulation System in MOTIS. IEEE Trans. on CAD of Integrated Circuits and Systems 6(2): 232-240 (1987)

Coauthor Index

1Robert M. Arlein [14]
2Charles H. Barry [16]
3Charles R. Bonapace [4] [11]
4Ajoy K. Bose [1]
5Chun-Yu Chen [20]
6Chung-Kuan Cheng [15] [18]
7Kuang-Wei Chiang [2] [3]
8Chi-Wen Deng [20]
9Debaprosad Dutt [10] [15] [18]
10Chi-Fu Huang [20]
11Chung-Ta King [20]
12Jeong-Tyng Li [7]
13Chun-Yu Lin [20]
14Jirí Matousek [12] [17]
15Surendra Nahar [2] [3] [15] [18]
16Hao N. Nham [1]
17Chong-Leong Ong [7]
18Nishit P. Parikh [8] [13]
19Jang-Ping Sheu [20]
20H. Shin [6]
21Anoop Singhal [8] [13] [14] [19]
22William L. Steiger [12] [17]
23Shun-Lin Su [16]
24Yu-Chee Tseng [20]
25Ravi Varadarajan [9]
26Chin-Hao Wu [20]
27Fang-Jing Wu [20]
28Kwok W. Wu [8] [13]
29Chien-Wen Yang [20]
30So-Zen Yao [15] [18]

Colors in the list of coauthors

Copyright © Sun Mar 14 22:39:24 2010 by Michael Ley (ley@uni-trier.de)