Volume 28,
Number 1,
January 1979
Correspondence
- Vinod K. Agarwal, Gerald M. Masson:
A Functional Form Approach to Test Set Coverage in Tree Networks.
50-52
- Y. Zisapel, M. Krieger, J. Kella:
Detection of Hazards in Combinational Switching Circuits.
52-56
- H. J. Trussel, Bobby R. Hunt:
Improved Methods of Maximum a Posteriori Restoration.
57-62
- Brian R. Gaines:
Maryanski's Grammatical Inferencer.
62-64
- Fred J. Maryanski, Taylor L. Booth:
Authors' Reply.
64
- Erkki Oja:
On the Construction of Projectors Using Products of Elementary Matrices.
65-66
- Tsutomu Sasao, Kozo Kinoshita:
On the Number of Fanout-Free Functions and Unate Cascade Functions.
66-72
- Mordechai Ben-Ari:
On Transposing Large 2n × 2n Matrices.
72-75
- Jay Niel Culliney, Ming Huei Young, T. Nakagawa, Saburo Muroga:
Results of the Synthesis of Optimal Networks of AND and OR Gates for Four-Variable Switching Functions.
76-85
- R. David, R. Tellez-Giron:
Comments on ``The Error Latency of a Fault in a Sequential Digital Circuit''.
85-86
Volume 28,
Number 2,
February 1979
Correspondence
Volume 28,
Number 3,
March 1979
Correspondence
Volume 28,
Number 4,
April 1979
Correspondence
Volume 28,
Number 5,
May 1979
Correspondence
- P. Ciompi, Luca Simoncini:
Analysis and Optimal Design of Self-Diagnosable Systems with Repair.
362-365
- Douglas Stott Parker Jr.:
Combinatorial Merging and Huffman's Algorithm.
365-367 ,
Correction:
IEEE Transactions on Computers 30(6):
454 (1981)
- Wolfgang Coy:
On the Design of Easily Testable Iterative Systems of Combinational Cells.
367-371
- Teruo Hikita, Hajime Enomoto:
On the Number of Multivalued Switching Functions Realizable by Cascades.
371-374
- James E. Smith:
Universal System Diagnosis Algorithms.
374-378
Volume 28,
Number 6,
June 1979
Volume 28,
Number 7,
July 1979
Correspondence
Volume 28,
Number 8,
August 1979
Correspondence
Volume 28,
Number 9,
September 1979
- Suhas S. Patil, Terry A. Welch:
A Programmable Logic Approach for VLSI.
594-601
- Roy A. Wood:
A High Density Programmable Logic Array Chip.
602-608
- Yahiko Kambayashi:
Logic Design of Programmable Logic Arrays.
609-617
- Daniel L. Ostapko, Se June Hong:
Fault Analysis and Test Generation for Programmable Logic Arrays (PLA's).
617-627
- Share Young Lee, Hsu Chang:
Associative-Search Bubble Devices for Content-Addressable Memory and Array Logic.
627-636
- Heinrich Pangratz, Hans Weinrichter:
Pseudo-Random Number Generator Based on Binary and Quinary Maximal-Length Sequences.
637-642
- Jon Louis Bentley, Thomas Ottmann:
Algorithms for Reporting and Counting Geometric Intersections.
643-647
- Hung Chi Lai, Saburo Muroga:
Minimum Parallel Binary Adders with NOR (NAND) Gates.
648-659
- Utpal Banerjee, Shyh-Ching Chen, David J. Kuck, Ross A. Towle:
Time and Parallel Processor Bounds for Fortran-Like Loops.
660-670
- Joseph Y.-T. Leung, Edmund K. Lai:
On Minimum Cost Recovery from System Deadlock.
671-677
- B. Ramakrishna Rau:
Interleaved Memory Bandwidth in a Model of a Muyltiprocessor Computer System.
678-681
Correspondence
Volume 28,
Number 10,
October 1979
- Andrew Hopper, David J. Wheeler:
Binary Routing Networks.
609-703
- Steven I. Kartashev, Svetlana P. Kartashev:
A Multicomputer System with Dynamic Architecture.
704-721
- I-Ngo Chen, Robert Willoner:
An 0(n) Parallel Multiplier with Bit-Sequential Input and Output.
721-727
- Yasuhito Suenaga, Takahiko Kamae, Tomonori Kobayashi:
A High-Speed Algorithm for the Generation of Straight Lines and Circular Arcs.
728-736
- Erol Gelenbe, Kenneth C. Sevcik:
Analysis of Update Synchronization for Multiple Copy Data Bases.
737-747
- John B. Kam, George I. Davida:
Structured Design of Substitution-Permutation Encryption Networks.
747-753
- Charles R. Kime:
An Abstract Model for Digital System Fault Diagnosis.
754-767
- Keijiro Nakamura:
Synthesis of Gate-Minimum Multi-Output Two-Level Negative Gate Networks.
768-772
- Edmund A. Lamagna:
The Complexity of Monotone Networks for Certain Bilinear Forms, Routing Problems, Sorting, and Merging.
773-782
- Teofilo F. Gonzalez:
A Note on Open Shop Preemptive Schedules.
782-786
Correspondence
- Pramod K. Varshney:
On Analytical Modeling of Intermittent Faults in Digital Systems.
786-791
- K. G. Kulkarni, V. Jayakumar:
Ordering of Connections for Automated Routing.
791-794
- Hans P. Moravec:
Fully Interconnecting Multiple Computers with Pipelined Sorting Nets.
795-798
- Anil K. Sarje, Nripendra N. Biswas:
A New Approach to 2-Asummability Testing.
798-801
- James E. Smith:
On Necessary and Sufficient Conditions for Multiple Fault Undetectability.
801-802
- Thomas J. Chaney:
Comments on ``A Note on Synchronizer or Interlock Maloperation''.
802-804
- E. Gordon Wormald:
Support for T. J. Chaney's Comments on ``A Note on Synchronizer or Interlock Maloperation''.
804
- Bella Bose:
Comments on ``Multiple Fault Detection in Combinational Network''.
804-805
Volume 28,
Number 11,
November 1979
Correspondence
Volume 28,
Number 12,
December 1979
Correspondence
Copyright © Mon Mar 15 04:06:53 2010
by Michael Ley (ley@uni-trier.de)
