8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China.
IEEE Computer Society 1999, ISBN 0-7695-0315-2 
@proceedings{DBLP:conf/ats/1999,
title = {8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai,
China},
booktitle = {Asian Test Symposium},
publisher = {IEEE Computer Society},
year = {1999},
isbn = {0-7695-0315-2},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
ATPG Related Approaches I
Delay Fault & Memory Test
ATPG Related Approaches II
- Shiyi Xu, Tukwasibwe Justaf Frank:
An Evaluation of Test Generation Algorithms for combinational Circuits.
63-69
- Zhide Zeng, Jihua Chen, Hefeng Cao:
Research and Implementation of a High Speed Test Generation for Ultra Large Scale Combinational Circuits.
70-74
- Irith Pomeranz, Sudhakar M. Reddy:
Pattern Sensitivity: A Property to Guide Test Generation for Combinational Circuits.
75-80
- Jing-Jou Tang:
An Accurate Logic Threshold Voltages Determination Model for CMOS Gates to Facilitate Test Generation and Fault Simulation.
81-
BIST Related Approaches
- Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption.
89-94
- Wenyi Feng, Wei-Kang Huang, Fred J. Meyer, Fabrizio Lombardi:
A BIST TPG Approach for Interconnect Testing With the IEEE 1149.1 STD.
95-100
- Albrecht P. Stroele, Frank Mayer:
Test Scheduling with Loop Folding and Its Application to Test Configurations with Accumulators.
101-106
- C. P. Ravikumar, Ashutosh Verma, Gaurav Chandra:
A Polynomial-Time Algorithm for Power Constrained Testing of Core Based Systems.
107-112
- Serge N. Demidenko, Kenneth V. Lever:
Accelerating Test Data Processin.
113-
Test Generation,
Diagnosis,
& Verification
IDDQ Test
- Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita:
Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits.
141-146
- Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara:
On an Effective Selection of IDDQ Measurement Vectors for Sequential Circuits.
147-152
- Junichi Hirase, Naoki Shindou, Kouji Akahori:
Scan Chain Diagnosis Using IDDQ Current Measurement.
153-157
- Arabi Keshk, Kozo Kinoshita, Yukiya Miura:
IDDQ Current Dependency on Test Vectors and Bridging Resistance.
158-163
- Tsuyoshi Shinogi, Terumine Hayashi:
A Parallel Generation System of Compact IDDQ Test Sets for Large Combinational Circuits.
164-
Sequential Circuit Test
Fault-Tolerant & Diagnosis
Analog Circuits Test
Railway Signaling Software
- Fangmei Wu, Meng Li:
Railway Signaling Safety-critical Software Testing Based on Dynamic Decision Table.
247-250
- Zhongwei Xu, Fangmei Wu:
A Novel Testing Approach for Safety-Critical Software.
251-255
- Haiying Tu, Fangmei Wu:
How to Design an Environment Simulator for Safety Critical Software Testing.
256-
DFT
Software Test & Verification
Scan & Boundary Scan
Beam Testing in Japan
- Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka:
Intelligent EB Test System for Automatic VLSI Fault Tracing.
335-341
- Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu, Nobuhiro Yanagida:
Multiple Fault Diagnosis in Logic Circuits Using EB Tester and Multiple/Single Fault Simulators.
341-346
- Reisuke Shimoda, Takaki Yoshida, Masafumi Watari, Yasuhiro Toyota, Kiyokazu Nishi, Akira Motohara:
Practical Application of Automated Fault Diagnosis for Stuck-at, Bridging, and Measurement Condition Dependent Faults in Fully Scanned Sequential Circuits.
347-
FPGA Test
Beam Testing in Japan
Copyright © Fri Mar 12 17:06:43 2010
by Michael Ley (ley@uni-trier.de)
