12. Asian Test Symposium 2003: Xian, China

@proceedings{DBLP:conf/ats/2003,
  title     = {12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian,
               China},
  booktitle = {Asian Test Symposium},
  publisher = {IEEE Computer Society},
  year      = {2003},
  isbn      = {0-7695-1951-2},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

Keynote Address

• Kewal K. Saluja:
  Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits. 2
  
• Yervant Zorian:
  Leveraging Infrastructure IP for SoC Yield. 3-5
  

Design for Testabilit

• Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita:
  Reducing Scan Shifts Using Folding Scan Trees. 6-11
  
• Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara:
  Improving Test Quality of Scan-Based BIST by Scan Chain Partitioning. 12-17
  
• Xiangdong Xuan, Abhijit Chatterjee, Adit D. Singh, Namsoo P. Kim, Mark T. Chisa:
  IC Reliability Simulator ARET and Its Application in Design-for-Reliability. 18-23
  

Memory Testing 1

• Zaid Al-Ars, A. J. van de Goor:
  Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance Traces. 24-27
  
• Yuki Yamagata, Kenichi Ichino, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Masayuki Satoh, Hiroyuki Itabashi, Takashi Murai, Nobuyuki Otsuka:
  Implementation of Memory Tester Consisting of SRAM-Based Reconfigurable Cells. 28-31
  
• Fabrizio Bertuccelli, Franco Bigongiari, Andrea S. Brogna, Giorgio Di Natale, Paolo Prinetto, Roberto Saletti:
  Exhaustive Test of Several Dependable Memory Architectures Designed by GRAAL Tool. 32-37
  

Fault Diagnosis 1

• Yu-Chiun Lin, Shi-Yu Huang:
  Chip-Level Diagnostic Strategy for Full-Scan Designs with Multiple Faults. 38-43
  
• Yu Huang, Wu-Tung Cheng, Cheng-Ju Hsieh, Huan-Yung Tseng, Alou Huang, Yu-Ting Hung:
  Efficient Diagnosis for Multiple Intermittent Scan Chain Hold-Time Faults. 44-49
  
• Xiaofan Yang:
  A Linear Time Fault Diagnosis Algorithm for Hypercube Multiprocessors under the MM* Comparison Model. 50-57
  

Delay Testing

• Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara:
  Reducibility of Sequential Test Generation to Combinational Test Generation for Several Delay Fault Models. 58-63
  
• Masayasu Fukunaga, Seiji Kajihara, Sadami Takeoka:
  On Estimation of Fault Efficiency for Path Delay Faults. 64-67
  
• Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara:
  Software-Based Delay Fault Testing of Processor Cores. 68-71
  
• Irith Pomeranz, Sudhakar M. Reddy:
  A DFT Approach for Path Delay Faults in Interconnected Circuits. 72-77
  

BIST

• Sukanta Das, Anirban Kundu, Subhayan Sen, Biplab K. Sikdar, Parimal Pal Chaudhuri:
  Non-Linear Celluar Automata Based PRPG Design (Without Prohibited Pattern Set) In Linear Time Complexity. 78-83
  
• Ehsan Atoofian, Zainalabedin Navabi:
  A BIST Architecture for FPGA Look-Up Table Testing Reduces Reconfigurations. 84-89
  
• Md. Rafiqul Islam, Hafiz Md. Hasan Babu, Mohammad Abdur Rahim Mustafa, Md. Sumon Shahriar:
  A Heuristic Approach for Design of Easily Testable PLAs Using Pass Transistor Logic. 90-95
  

Software Testing 1

• Ruilian Zhao, Michael R. Lyu, Yinghua Min:
  Domain Testing Based on Character String Predicate. 96-101
  
• Matthias Beyer, Winfried Dulz, Fenhua Zhen:
  Automated TTCN-3 Test Case Generation by Means of UML Sequence Diagrams and Markov Chains. 102-105
  
• Fangmei Wu, Lei Huang:
  Efficiency Analysis and Safety Assessment of Automatic Testing for Safety-Critical Software. 106-109
  
• Yunzhan Gong, Wanli Xu, Xiaowei Li:
  An Expression's Single Fault Model and the Testing Methods. 110-115
  

Mixed-Signal Testing

• Jayasanker Jayabalan, Chee Kiang Goh, Ooi Ban Leong, Leong Mook Seng, Mahadevan K. Iyer, Andrew A. O. Tay:
  PLL Based High Speed Functional Testing. 116-119
  
• Mike W. T. Wong:
  Issues Related to the Formulation of DFT Solution for Analog Circuit Test Using Equivalent Fault Analysis. 120-123
  
• Kuen-Jong Lee, Soon-Jyh Chang, Ruei-Shiuan Tzeng:
  A Sigma-Delta Modulation Based BIST Scheme for A/D Converters. 124-129
  

Test Compaction 1

• Toshinori Hosokawa, Hiroshi Date, Masahide Miyazaki, Michiaki Muraoka, Hideo Fujiwara:
  A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint. 130-135
  
• Kohei Miyase, Seiji Kajihara:
  Optimal Scan Tree Construction with Test Vector Modification for Test Compression. 136-141
  
• Bernd Koenemann:
  STAGE: A Decoding Engine Suitable for Multi-Compressed Test Data. 142-147
  

RTL Verification

• Liang Zhang, Michael S. Hsiao, Indradeep Ghosh:
  Automatic Design Validation Framework for HDL Descriptions via RTL ATPG. 148-153
  
• Tun Li, Yang Guo, Sikun Li:
  An Automatic Circuit Extractor for RTL Verification. 154-160
  
• Tao Lv, Jianping Fan, Xiaowei Li:
  An Efficient Observability Evaluation Algorithm Based on Factored Use-Def Chains. 161-167
  

Enhanced Delay Testing and ATPG

• Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand:
  Delay Testing of MOS Transistor with Gate Oxide Short. 168-173
  
• Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer:
  An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults. 174-177
  
• Huawei Li, Yue Zhang, Xiaowei Li:
  Delay Test Pattern Generation Considering Crosstalk-Induced Effects. 178-183
  
• Magdy S. Abadir, Jing Zeng, Carol Pyron, Juhong Zhu:
  Automated Test Model Generation from Switch Level Custom Circuits. 184-189
  

Test Power

• Samir Roy, Biplab K. Sikdar:
  Power Conscious BIST Design for Sequential Circuits Using ghost-FSM. 190-195
  
• Yongjun Xu, Zuying Luo, Zhiguo Chen, Xiaowei Li:
  Average Leakage Current Macromodeling for Dual-Threshold Voltage Circuits. 196-201
  
• Ozgur Sinanoglu, Alex Orailoglu:
  Test Data Manipulation Techniques for Energy-Frugal, Rapid Scan Test. 202-209
  

Software Testing 2

• Masayuki Hirayama, Tetsuya Yamamoto, Osamu Mizuno, Tohru Kikuno:
  Analysis of Software Test Item Generation - Comparison between High Skilled and Low Skilled Engineers. 210-215
  
• Chang Xu, Beihong Jin:
  Conformance Test of Distributed Transaction Service. 216-219
  
• Shiyi Xu:
  Build-In-Self-Test for Software. 220-223
  
• Hui-Qun Zhao, Qin-Xin Gao, Yuan Gao:
  Testing the Conformity of Transactional Attributes of Components by Simulation. 224-229
  

Fault Diagnosis

• Baris Arslan, Alex Orailoglu:
  Extracting Precise Diagnosis of Bridging Faults from Stuck-at Fault Information. 230-235
  
• Xiaoqing Wen, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita:
  Fault Diagnosis for Physical Defects of Unknown Behaviors. 236-241
  
• Pan Zhongliang:
  Fault Detection for Testable Realizations of Multiple-Valued Logic Functions. 242-249
  

Memory Testing 2

• Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri:
  Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders. 250-255
  
• Rei-Fu Huang, Yung-Fa Chou, Cheng-Wen Wu:
  Defect Oriented Fault Analysis for SRAM. 256-261
  
• L. Kalyan Kumar, Amol J. Mupid, Aditya S. Ramani, V. Kamakoti:
  A Novel Method for Online In-Place Detection and Location of Multiple Interconnect Faults in SRAM Based FPGAs. 262-267
  

SOC Test

• Tsuyoshi Shinogi, Yuki Yamada, Terumine Hayashi, Tomohiro Yoshikawa, Shinji Tsuruoka:
  Between-Core Vector Overlapping for Test Cost Reduction in Core Testing. 268-273
  
• Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi:
  The VPI-Based Combinational IP Core Module-Based Mixed Level Serial Fault Simulation and Test Generation Methodology. 274-277
  
• Zhigang Jiang, Sandeep K. Gupta:
  A Test Generation Approach for Systems-on-Chip that Use Intellectual Property Cores. 278-283
  

DFT Synthesis

• Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya:
  Mapping Symmetric Functions to Hierarchical Modules for Path-Delay Fault Testability. 284-289
  
• Junhao Shi, Görschwin Fey, Rolf Drechsler:
  BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability. 290-293
  
• Michiko Inoue, Kazuhiro Suzuki, Hiroyuki Okamoto, Hideo Fujiwara:
  Test Synthesis for Datapaths Using Datapath-Controller Functions. 294-299
  
• Dong Xiang, Shan Gu, Hideo Fujiwara:
  Non-Scan Design for Testability for Mixed RTL Circuits with Both Data Paths and Controller via Conflict Analysis. 300-305
  

Test Scheduling

• Erik Larsson, Hideo Fujiwara:
  Optimal System-on-Chip Test Scheduling. 306-311
  
• Julien Pouget, Erik Larsson, Zebo Peng:
  SOC Test Time Minimization Under Multiple Constraints. 312-317
  
• Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin:
  Test Time Minimization for Hybrid BIST of Core-Based Systems. 318-325
  

Measurement

• Tian Xia, Jien-Chung Lo:
  On-Chip Short-Time Interval Measurement for High-Speed Signal Timing Characterization. 326-331
  
• Chin-Cheng Tsai, Chung-Len Lee:
  An On-Chip Jitter Measurement Circuit for the PLL. 332-335
  
• Jui-Jer Huang, Jiun-Lang Huang:
  A Low-Cost Jitter Measurement Technique for BIST Applications. 336-339
  
• Junfeng Wang, Jianhua Yang, Gaogang Xie, Mingtian Zhou, Zhongcheng Li:
  Measurement-Based Modeling with Adaptive Sampling. 340-347
  

Test Economics

• Baosheng Wang, Yong B. Cho, Sassan Tabatabaei, André Ivanov:
  Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device Testing. 348-353
  
• Yuxin Tian, Michael R. Grimaila, Weiping Shi, M. Ray Mercer:
  Minimizing Defective Part Level Using a Linear Programming-Based Optimal Test Selection Method. 354-359
  
• Jochen Rivoir:
  Lowering Cost of Test: Parallel Test or Low-Cost ATE? 360-365
  

Memory Testing 3

• Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu:
  A Processor-Based Built-In Self-Repair Design for Embedded Memories. 366-371
  
• Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mike Rodgers:
  March SL: A Test For All Static Linked Memory Faults. 372-377
  
• Xiaogang Du, Sudhakar M. Reddy, Joseph Rayhawk, Wu-Tung Cheng:
  Testing Delay Faults in Embedded CAMs. 378-383
  
• Mohammad Gh. Mohammad, Kewal K. Saluja:
  Stress Test for Disturb Faults in Non-Volatile Memories. 384-389
  

Current Test

• Masaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura, Kozo Kinoshita:
  A BIST Circuit for IDDQ Tests. 390-395
  
• Yinghua Min, Jishun Kuang, Xiaoyan Niu:
  At-Speed Current Testing. 396-399
  
• Jishun Kuang, Yu Wang, Xiaofen Wei, Changnian Zhang:
  IDDT ATPG Based on Ambiguous Delay Assignments. 400-405
  
• Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Toshifumi Kobayashi, Tsutomu Hondo:
  Improvement of Detectability for CMOS Floating Gate Defects in Supply Current Test. 406-411
  

SOC DFT

• Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara:
  A DFT Selection Method for Reducing Test Application Time of System-on-Chips. 412-417
  
• Huaguo Liang, Cuiyun Jiang:
  Sharing BIST with Multiple Cores for System-on-a-Chip. 418-423
  
• Md. Saffat Quasem, Sandeep K. Gupta:
  Designing Multiple Scan Chains for Systems-on-Chip. 424-427
  
• Yingxiang Wang, Weikang Huang:
  Optimizing Test Access Mechanism under Constraints by Genetic Local Search Algorithm. 428-433
  

Test Compaction 2

• Irith Pomeranz, Sudhakar M. Reddy:
  Test Data Volume Reduction by Test Data Realignment. 434-439
  
• Yinhe Han, Yongjun Xu, Huawei Li, Xiaowei Li, Anshuman Chandra:
  Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Teste. 440-445
  
• Hideyuki Ichihara, Michihiro Shintani, Toshihiro Ohara, Tomoo Inoue:
  Test Response Compression Based on Huffman Coding. 446-451
  

Functional Testing/Reliability

• Gaocai Wang, Jianer Chen, Guojun Wang, Songqiao Chen:
  Probability Model for Faults in Large-Scale Multicomputer Systems. 452-457
  
• Ling Liu, Wennan Feng, Song Jia, Anping Jiang, Lijiu Ji:
  Design Retargetable Platform System for Microprocessor Functional Test. 458-461
  
• Piotr Gawkowski, Janusz Sosnowski:
  Assessing Software Implemented Fault Detection and Fault Tolerance Mechanisms. 462-467
  
• Fabian Vargas, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr., Diogo B. Brum:
  Briefing a New Approach to Improve the EMI Immunity of DSP Systems. 468-473
  

Formal Verification

• Guanghui Li, Ming Shao, Xiaowei Li:
  Design Error Diagnosis Based on Verification Techniques. 474-477
  
• Ming Shao, Guanghui Li, Xiaowei Li:
  SAT-Based Algorithm of Verification for Port Order Fault. 478-481
  
• Zhan Xu, Xiaolang Yan, Yongjiang Lu, Haitong Ge:
  Equivalence Checking Using Independent Cuts. 482-487
  

Software Testing 3

• Yuan Zhu, Jianhua Gao:
  A Method to Calculate the Reliability of Component-Based Software. 488-491
  
• Da-Hai Jin, Yun-Zhan Gong:
  An Object-Oriented Program Automatic Execute Model and the Research of Algorithm. 492-495
  
• Jin-Min Yang, Da-Fang Zhang, Xue Dong Yang:
  User-Level Implementation of Checkpointing for Multithreaded Applications on Windows NT. 496-501
  

Poster Session

• Li Shen:
  RTL Concurrent Fault Simulation. 502
  
• Ming Zhu, Jinian Bian, Weimin Wu, Hongxi Xue:
  Property Classification for Functional Verification Based. 503
  
• Jian-Hui Jiang:
  Error Detection and Correction in VLSI Systems by Online Testing and Retrying. 504
  
• Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jahangir:
  Testability Improvement During High-Level Synthesis. 505
  
• Yong-sheng Wang, Liyi Xiao, Mingyan Yu, Jinxiang Wang, Yizheng Ye:
  A Test Architecture for System-on-a-Chip. 506
  
• He Hu, Yihe Sun:
  Test-Point Selection Algorithm Using Small Signal Model for Scan-Based BIST. 507
  
• Junichi Hirase:
  Test Pattern Length Required to Reach the Desired Fault Coverage. 508
  
• Zhongwei Xu, Bangxing Chen:
  Damage Size and Software Safety Demonstration Stress Testing. 509
  
• Meng Li, Zhu Xu:
  Study on the Cost/Benefit/Optimization of Software Safety Test. 510