10. ISCA 1983: Stockholm, Sweden
Proc. 10th Annual Symposium on Computer Architecture.
1983 
- Maurice V. Wilkes:
Size, Power, and Speed.
2-4
- Wolfgang K. Giloi:
Towards a Taxonomy of Computer Architecture Based on the Machine Data Type View.
6-15
- Algirdas Avizienis:
Frameworks for a Taxonomy of Fault-Tolerance Attributes in Computer Systems.
16-21
- Björn Pehrson, Joachim Parrow:
Caddie - An Interactive Design Environment.
24-31
- Subrata Dasgupta:
On the Verification of Computer Architectures Using an Architecture Description Language.
32-38
- Richard M. King:
Research on Synthesis of Concurrent Computing Systems.
39-46
- Allan L. Fisher, H. T. Kung, Louis Monier, Yasunori Dohi:
Architecture of the PSC: A Programmable Systolic Chip.
48-53
- Allan L. Fisher, H. T. Kung:
Synchronizing Large VLSI Processor Arrays.
54-58
- Robert A. Wagner:
The Boolean Vector Machine [BVM].
59-66
- Maurizio A. Bonuccelli, Elena Lodi, Fabrizio Luccio, Piero Maestrini, Linda Pagli:
A VLSI Tree Machine for Relational Data Bases.
67-73
- L. J. Caluwaerts, J. Debacker, J. A. Peperstraete:
Implementing Streams on a Data Flow Computer System With Paged Memory.
76-83
- Joseph E. Requa:
The Piecewise Data Flow Architecture Control Flow and Register Management.
84-89
- Mario Tokoro, J. R. Jagannathan, Hideki Sunahara:
On the Working Set Concept for Data-Flow Machines.
90-97
- R. W. Marczynski, J. Milewski:
A Data Driven System Based on a Microprogrammed Processor Module.
98-106
- David A. Patterson, Phil Garrison, Mark D. Hill, Dimitris Lioupis, Chris Nyberg, Tim Sippel, Korbin Van Dyke:
Architecture of a VLSI Instruction Cache for a RISC.
108-116
- Phil C. C. Yeh, Janak H. Patel, Edward S. Davidson:
Performance of Shared Cache for Parallel-Pipelined Computer Systems.
117-123
- James R. Goodman:
Using Cache Memory to Reduce Processor-Memory Traffic.
124-131
- James E. Smith, James R. Goodman:
A Study of Instruction Cache Organizations and Replacement Policies.
132-137
- Joseph A. Fisher:
Very Long Instruction Word Architectures and the ELI-512.
140-150
- Shinji Tomita, Kiyoshi Shibayama, Toshiaki Kitamura, Toshiyuki Nakata, Hiroshi Hagiwara:
A User-Microprogrammable, Local Host Computer With Low-Level Parallelism.
151-157
- Richard H. Gumpertz:
Combining Tags With Error Codes.
160-165
- Young Gil Park, Jung Wan Cho:
Fault Diagnosis of Bit-Slice Processor.
166-172
- Miguel Angel Fiol, Ignacio Alegre, J. Luis A. Yebra:
Line Digraph Iterations and the (d,k) Problem for Directed Graphs.
174-177
- Eli Opper, Miroslaw Malek, G. Jack Lipovski:
Resource Allocation in Rectangular CC-Banyans.
178-184
- Frantisek Sovis:
Uniform Theory of the Shuffle-Exchange Type Permutation Networks.
185-191
- Vason P. Srini, Jorge F. Asenjo:
Analysis of Cray-1S Architecture.
194-206
- Harry F. Jordan:
Performance Measurements on HEP - A Pipelined MIMD Computer.
207-212
- Hideharu Amano, Takaichi Yoshida, Hideo Aiso:
(SM)2: Sparse Matrix Solving Machine.
213-220
- R. Kalyana Krishnan, A. K. Rajasekar, C. S. Moghe:
An Experimental System for Computer Science Instruction.
222-227
- Klaus Kronlof:
Execution Control and Memory Management of a Data Flow Signal Processor.
230-235
- Masasuke Kishi, Hiroshi Yasuhara, Yasusuke Kawamura:
DDDP: A Distributed Data Driven Processor.
236-242
- Naohisa Takahashi, Makoto Amamiya:
A Data Flow Processor Array System: Design and Analysis.
243-250
- Kenneth A. Pier:
A Retrospective on the Dorado, A High-Performance Personal Computer.
252-269
- Robert J. Dugan:
System/370 Extended Architecture: A Program View of the Channel Subsystem.
270-276
- Richard L. Norton, Jacob A. Abraham:
Adaptive Interpretation as a Means of Exploiting Complex Instruction Sets.
277-282
- Manoj Kumar, Daniel M. Dias, J. Robert Jump:
Switching Strategies in a Class of Packet Switching Networks.
284-300
- Benjamin W. Wah:
A Comparative Study of Distributed Resource Sharing on Multiprocessors.
301-308
- W. Kent Fuchs, Jacob A. Abraham, Kuang-Hua Huang:
Concurrent Error Detection in VLSI Interconnection Networks.
309-315
- Wolfgang K. Giloi, Peter M. Behr:
Hierarchical Function Distribution - A Design Principle for Advanced Multicomputer Architectures.
318-325
- Luigi Stringa:
EMMA: An Industrial Experience on Large Multiprocessing Architectures.
326-333
- Lars Philipson, Bo Nilsson, Bjorn Breidegard:
A Communication Structure for a Multiprocessor Computer with Distributed Global Memory.
334-340
- Hiromu Hayashi, Akira Hattori, Haruo Akimoto:
ALPHA: A High-Performance LISP Machine Equipped with a New Stack Structure and Garbage Collection System.
342-348
- Shinji Umeyama, Koichiro Tamura:
A Parallel Execution Model of Logic Programs.
349-355
- Claudia Schmittgen, Werner E. Kluge:
A System Architecture for the Concurrent Evaluation of Applicative Program Expressions.
356-362
- Yoshinori Yamaguchi, Kenji Toda, Toshitsugu Yuba:
A Performance Evaluation of a Lisp-Based Data-Driven Machine (EM-3).
363-369
- Steven L. Tanimoto:
A Pyramidal Approach to Parallel Processing.
372-378
- Gerard Gaillat:
The Design of a Parallel Processor for Image Processing On-Board Satellites: An Application Oriented Approach.
372-386
- Hitoshi Nishimura, Hiroshi Ohno, Toru Kawata, Isao Shirakawa, Koichi Omura:
LINKS-1: A Parallel Pipelined Multimicrocomputer System for Image Creation.
387-394
- T. Ericsson, Per-Erik Danielsson:
LIPP-A SIMD Multiprocessor Architecture for Image Processing.
395-400
- Philip C. Treleaven:
The New Generation of Computer Architecture.
402-409
- Shunichi Uchida:
Inference Machine: From Sequential to Paralle.
410-416
- Tohru Moto-Oka:
Overview to the Fifth Generation Computer System Project.
417-422
- Kunio Murakami, Takeo Kakuta, Nobuyoshi Miyazaki, Shigeki Shibayama, Haruo Yokota:
A Relational Data Base Machine: First Step to Knowledge Base Machine.
423-425
- Arvind, Robert A. Iannucci:
A Critique of Multiprocessing von Neumann Style.
426-436
Copyright © Fri Mar 12 17:16:44 2010
by Michael Ley (ley@uni-trier.de)
