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@inproceedings{DBLP:conf/vldb/Tanaka84,
author = {Yuzuru Tanaka},
editor = {Umeshwar Dayal and
Gunter Schlageter and
Lim Huat Seng},
title = {Bit-Sliced VLSI Algorithm for Search and Sort},
booktitle = {Tenth International Conference on Very Large Data Bases, August
27-31, 1984, Singapore, Proceedings},
publisher = {Morgan Kaufmann},
year = {1984},
isbn = {0-934613-16-8},
pages = {225-234},
ee = {db/conf/vldb/Tanaka84.html},
crossref = {DBLP:conf/vldb/84},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
For the high speed processing of databases, it is fundamental to introduce various VLSI architectures to the processing of basic functions. Especially, sort and batch search requires high speed modules. The VLSI algorithms of them must make use of the time necessary for the transfer of a large amount of data to and from the modules. These modules should be nonprogrammable in order to avoid serious overheads. However, they should be able to extend their capacity and wordlength by the connection of them.
This paper solves the problem of how to extend the wordlength of search and sort hardware modules. It proposes bit-sliced architectures of an interval search engine and a two-way-merge sorter. The slicing of these engines does not cause excessive overheads. The decrease of the slice length decreases the hardware complexity, and increases the flexibility of the modules. Therefore, it increases the feasibility of the VLSI implementation of these hardware modules.
Copyright © 1984 by the VLDB Endowment. Permission to copy without fee all or part of this material is granted provided that the copies are not made or distributed for direct commercial advantage, the VLDB copyright notice and the title of the publication and its date appear, and notice is given that copying is by the permission of the Very Large Data Base Endowment. To copy otherwise, or to republish, requires a fee and/or special permission from the Endowment.
