31. DAC 1994: San Diego, California, USA

Software & Instruction Set Synthesis

• Pai H. Chou, Gaetano Borriello:
  Software Scheduling in the Co-Synthesis of Reactive Real-Time Systems. 1-4
  
• Ing-Jer Huang, Alvin M. Despain:
  Synthesis of Instruction Sets for Pipelined Microprocessors. 5-11
  

Transition Densities for Sequential Systems

• José C. Monteiro, Srinivas Devadas, Bill Lin:
  A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits. 12-17
  
• Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain:
  Exact and Approximate Methods for Calculating Signal and Transition Probabilities in FSMs. 18-23
  

CAD for Analog and High-Performance Digital Circuits

• Emil S. Ochotta, Rob A. Rutenbar, L. Richard Carley:
  ASTRX/OBLX: Tools for Rapid Synthesis of High-Performance Analog Circuits. 24-30
  
• Edoardo Charbon, Enrico Malavasi, Davide Pandini, Alberto L. Sangiovanni-Vincentelli:
  Simultaneous Placement and Module Optimization of Analog IC's. 31-35
  
• Sharad Mehrotra, Paul D. Franzon, Wentai Liu:
  Stochastic Optimization Approach to Transistor Sizing for CMOS VLSI Circuits. 36-40
  

Management of Electronic Design Automation

• Ajit M. Prabhu:
  Management Issues in Eda. 41-47
  

Panel

• Joseph B. Costello, Walden C. Rhines, Aart J. de Geus, Alain Hanover, Doug Fairbairn, Rick Carlson, Ronald Collett:
  Executive Perspective and Vision of the Future of EDA (Panel). 48
  

Asynchronous Synthesis

• Gjalt G. de Jong, Bill Lin:
  A Communicating Petri Net Model for the Design of Concurrent Asynchronous Modules. 49-55
  
• Alex Kondratyev, Michael Kishinevsky, Bill Lin, Peter Vanbekbergen, Alexandre Yakovlev:
  Basic Gate Implementation of Speed-Independent Circuits. 56-62
  
• Ruchir Puri, Jun Gu:
  A Modular Partitioning Approach for Asynchronous Circuit Synthesis. 63-69
  
• Christian D. Nielsen, Michael Kishinevsky:
  Performance Analysis Based on Timing Simulation. 70-76
  

New Developments in Design for Test

• Pranav Ashar, Sharad Malik:
  Implicit Computation of Minimum-Cost Feedback-Vertex Sets for Partial Scan and Other Applications. 77-80
  
• Srimat T. Chakradhar, Arun Balakrishnan, Vishwani D. Agrawal:
  An Exact Algorithm for Selecting Partial Scan Flip-Flops. 81-86
  
• Srimat T. Chakradhar, Sujit Dey:
  Resynthesis and Retiming for Optimum Partial Scan. 87-93
  
• Wen-Chang Fang, Sandeep K. Gupta:
  Clock Grouping: A Low Cost DFT Methodology for Delay Testing. 94-99
  

Timing Analysis

• William K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
  Exact Minimum Cycle Times for Finite State Machines. 100-105
  
• Elizabeth A. Walkup, Gaetano Borriello:
  Interface Timing Verification with Application to Synthesis. 106-112
  
• Anurag P. Gupta, Daniel P. Siewiorek:
  Automated Multi-Cycle Symbolic Timing Verification of Microprocessor-Based Designs. 113-119
  
• Ajay J. Daga, William P. Birmingham:
  The Minimization and Decomposition of Interface State Machines. 120-125
  
• Horng-Fei Jyu, Sharad Malik:
  Statistical Delay Modeling in Logic Design and Synthesis. 126-130
  

Managing The Design Process

• Sean Murphy:
  Partnering with EDA Vendors: Tips, Techniques, and the Role of Standards. 131-134
  
• Wojciech Maly:
  Cost of Silicon Viewed from VLSI Design Perspective. 135-142
  

Estimation & Synthesis of Memory Structures

• Ingrid Verbauwhede, Chris J. Scheers, Jan M. Rabaey:
  Memory Estimation for High Level Synthesis. 143-148
  
• David J. Kolson, Alexandru Nicolau, Nikil D. Dutt:
  Minimization of Memory Traffic in High-Level Synthesis. 149-154
  
• Mohammed Aloqeely, C. Y. Roger Chen:
  Sequencer-Based Data Path Synthesis of Regular Iterative Algorithms. 155-160
  

Intellectual Property

• Dennis S. Fernandez:
  Intellectual Property Protection in the EDA Industry. 161-163
  

Panel

• William M. van Cleemput, Ewald Detjens, Herman Beke, George C. Chen, Joseph Hustein, William Lattin, Dennis S. Fernandez:
  Software Patents and Their Potential Impact on the EDA Community (Panel). 164
  

Technology-Driven Routing

• Kai Zhu, D. F. Wong:
  Switch Bound Allocation for Maximizing Routability in Timing-Driven Routing of FPGAs. 165-170
  
• Yachyang Sun, C. L. Liu:
  Routing in a New 2-Dimensional FPGA/FPIC Routing Architecture. 171-176
  
• Ikuo Harada, Hitoshi Kitazawa:
  A Global Router Optimizing Timing and Area for High-Speed Bipolar LSI's. 177-181
  
• Sreekrishna Madhwapathy, Naveed A. Sherwani, Siddharth Bhingarde, Anand Panyam:
  A Unified Approach to Multilayer Over-the-Cell Routing. 182-187
  

Panel

• Geoffrey Bunza, Steve Schulz, Tommy Jansson, Alex Silbey, Steve Ma, Edward H. Frank:
  PESDA and Design Abstraction: How High is Up? (Panel). 188
  

data-Path Synthesis & Test

• Miodrag Potkonjak, Mani B. Srivastava, Anantha Chandrakasan:
  Efficient Substitution of Multiple Constant Multiplications by Shifts and Additions Using Iterative Pairwise Matching. 189-194
  
• Subhrajit Bhattacharya, Sujit Dey, Franc Brglez:
  Clock Period Optimization During Resource Sharing and Assignment. 195-200
  
• Miodrag Potkonjak, Sujit Dey:
  Optimizing Resource Utilization and Testability Using Hot Potato Techniques. 201-205
  
• Ian G. Harris, Alex Orailoglu:
  Microarchitectural Synthesis of VLSI Designs with High Test Concurrency. 206-211
  

Topics in Verification and Diagnosis

• Masahiro Tomita, Tamotsu Yamamoto, Fuminori Sumikawa, Kotaro Hirano:
  Rectification of Multiple Logic Design Errors in Multiple Output Circuits. 212-217
  
• Andreas Kuehlmann, David Ihsin Cheng, Arvind Srinivasan, David P. LaPotin:
  Error Diagnosis for Transistor-Level Verification. 218-224
  
• Thomas R. Shiple, Ramin Hojati, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton:
  Heuristic Minimization of BDDs Using Don't Cares. 225-231
  

FPGA Partitioning and Optimization

• Kai Zhu, D. F. Wong:
  Clock Skew Minimization During FPGA Placement. 232-237
  
• Roman Kuznar, Franc Brglez, Baldomir Zajc:
  Multi-way Netlist Partitioning into Heterogeneous FPGAs and Minimization of Total Device Cost and Interconnect. 238-243
  
• Nan-Chi Chou, Lung-Tien Liu, Chung-Kuan Cheng, Wei-Jin Dai, Rodney Lindelof:
  Circuit Partitioning for Huge Logic Emulation Systems. 244-249
  

Design Implementation

• Pravil Gupta, Chih-Tung Chen, J. C. DeSouza-Batista, Alice C. Parker:
  Experience with Image Compression Chip Design using Unified System Construction Tools. 250-256
  
• Wang Tek Kee, Dennis Sng, Jacob Gan, Low Kin Kiong:
  The Use of CAD Frameworks in a CIM Environment. 257-261
  
• Hidekazu Terai, Kazutoshi Gemma, Yohsuke Nagao, Yasuo Satoh, Yasuhiro Ohno:
  Basic Concept of Cooperative Timing-driven Design Automation Technology for High-speed RISC Processor HARP-1. 262-269
  

BDD Techniques and Formal Verification

• Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi:
  Probabilistic Analysis of Large Finite State Machines. 270-275
  
• Alan J. Hu, Gary York, David L. Dill:
  New Techniques for Efficient Verification with Implicitly Conjoined BDDs. 276-282
  
• Adnan Aziz, Serdar Tasiran, Robert K. Brayton:
  BDD Variable Ordering for Interacting Finite State Machines. 283-288
  
• Gianpiero Cabodi, Paolo Camurati, Stefano Quer:
  Auxiliary Variables for Extending Symbolic Traversal Techniques to Data Paths. 289-293
  

Panel

• Jacob A. Abraham, Sandip Kundu, Janak H. Patel, Manuel A. d'Abreu, Bulent I. Dervisoglu, Marc E. Levitt, Hector R. Sucar, Ron G. Walther:
  Microprocessor Testing: Which Technique is Best? (Panel). 294
  

FPGA Placement & Routing

• Sanko Lan, Avi Ziv, Abbas El Gamal:
  Placement and Routing for a Field Programmable Multi-Chip Module. 295-300
  
• Sudip Nag, Rob A. Rutenbar:
  Performance-Driven Simultaneous Place and Route for Row-Based FPGAs. 301-307
  
• Shih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, Malgorzata Marek-Sadowska:
  Layout Driven Logic Synthesis for FPGAs. 308-313
  

Formal Verification

• Kenneth L. McMillan:
  Fitting Formal Methods into the Design Cycle. 314-319
  

Panel

• Ronald Collett, Mike Gianfagna, Michel Courtoy, Martin Baynes, Johan Van Ginderdeuren, Kenneth L. McMillan, Stephen Ricca, Alberto L. Sangiovanni-Vincentelli, Steve Sapiro, Naeem Zafar:
  Panel: Complex System Verification: The Challenge Ahead. 320
  

Layout and Technology Dependent Synthesis

• Andisheh Sarabi, Ning Song, Malgorzata Chrzanowska-Jeske, Marek A. Perkowski:
  A Comprehensive Approach to Logic Synthesis and Physical Design for Two-Dimensional Logic Arrays. 321-326
  
• Lalgudi N. Kannan, Peter Suaris, Hong-Gee Fang:
  A Methodology and Algorithms for Post-Placement Delay Optimization. 327-332
  
• Sasan Iman, Massoud Pedram, Kamal Chaudhary:
  Technology Mapping Using Fuzzy Logic. 333-338
  
• Chien-Chung Tsai, Malgorzata Marek-Sadowska:
  Boolean Matching Using Generalized Reed-Muller Forms. 339-344
  

Delay and Self Test

• Ishwar Parulkar, Melvin A. Breuer, Charles Njinda:
  Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST. 345-356
  
• Krishnendu Chakrabarty, John P. Hayes:
  DFBT: A Design-for-Testability Method Based on Balance Testing. 351-357
  
• Irith Pomeranz, Sudhakar M. Reddy:
  Design-for-Testability for Path Delay Faults in Large Combinatorial Circuits Using Test-Points. 358-364
  
• Kwang-Ting Cheng, Hsi-Chuan Chen:
  Generation of High Quality Non-Robust Tests for Path Delay Faults. 365-369
  
• Jui-Ching Shyur, Hung-Pin Chen, Tai-Ming Parng:
  On Testing Wave Pipelined Circuits. 370-374
  

Routing for High Performance

• Masato Edahiro:
  An Efficient Zero-Skew Routing Algorithm. 375-380
  
• Kenneth D. Boese, Andrew B. Kahng, Bernard A. McCoy, Gabriel Robins:
  Rectilinear Steiner Trees with Minimum Elmore Delay. 381-386
  
• Sachin S. Sapatnekar:
  RC Interconnect Optimization Under the Elmore Delay Model. 387-391
  
• Ashok Vittal, Malgorzata Marek-Sadowska:
  Minimal Delay Interconnect Design Using Alphabetic Trees. 392-396
  
• Qiong Yu, Sandeep Badida, Naveed A. Sherwani:
  Algorithmic Aspects of Three Dimensional MCM Routing. 397-401
  
• Hua Xue, Ed P. Huijbregts, Jochen A. G. Jess:
  Routing for Manufacturability. 402-406
  

Panel

• Andrew J. Graham, Richard Goldman, Wen-Tsuen Chen, Kerry Hanson, Nikolay G. Malishev, Shin-ichi Nakayama:
  Technology Summit - A View from the Top (Panel). 407
  

Logic Synthesis

• Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
  Optimum Functional Decomposition Using Encoding. 408-414
  
• Rolf Drechsler, Andisheh Sarabi, Michael Theobald, Bernd Becker, Marek A. Perkowski:
  Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams. 415-419
  
• Shin-ichi Minato:
  Calculation of Unate Cube Set Algebra Using Zero-Suppressed BDDs. 420-424
  
• Alexander Saldanha, Heather Harkness, Patrick C. McGeer, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
  Performance Optimization Using Exact Sensitization. 425-429
  
• Kazuo Iwama, Kensuke Hino:
  Random Generation of Test Instances for Logic Optimizers. 430-434
  

Tutorial: Hardware-Software Co-Design

• Kurt Keutzer:
  Hardware-Software Co-Design and ESDA. 435-436
  
• Asawaree Kalavade, Edward A. Lee:
  Manifestations of Heterogeneity in Hardware/Software Co-Design. 437-438
  
• James A. Rowson:
  Hardware/Software Co-Simulation. 439-440
  

Design Representations and Data Structures for High Level Design

• S. C. Prasad, P. Anirudhan, Patrick W. Bosshart:
  A System for Incremental Synthesis to Gate-Level and Reoptimization Following RTL Design Changes. 441-446
  
• Oz Levia, Serge Maginot, Jacques Rouillard:
  Lessons in Language Design: Cost/Benefit analysis of VHDL Features. 447-453
  
• Adnan Aziz, Felice Balarin, Szu-Tsung Cheng, Ramin Hojati, Timothy Kam, Sriram C. Krishnan, Rajeev K. Ranjan, Thomas R. Shiple, Vigyan Singhal, Serdar Tasiran, Huey-Yih Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
  HSIS: A BDD-Based Environment for Formal Verification. 454-459
  

Design Methodology

• P. H. Kelly, Kevin J. Page, Paul M. Chau:
  Rapid Prototyping of ASIC Based Systems. 460-465
  
• Polen Kission, Hong Ding, Ahmed Amine Jerraya:
  Structured Design Methodology for High-Level Design. 466-471
  
• Reid A. Baldwin, Moon-Jung Chung:
  Design Methodology Management Using Graph Grammars. 472-478
  

Scheduling

• Ivan P. Radivojevic, Forrest Brewer:
  Incorporating Speculative Execution in Exact Control-Dependent Scheduling. 479-484
  
• Nelson L. Passos, Edwin Hsing-Mean Sha, Steven C. Bass:
  Loop Pipelining for Scheduling Multi-Dimensional Systems via Rotation. 485-490
  
• Subhrajit Bhattacharya, Sujit Dey, Franc Brglez:
  Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications. 491-496
  

CAD Algorithms in Non-CAD Problems

• Maria Domenica Di Benedetto, Pasquale Lucibello, Alberto L. Sangiovanni-Vincentelli, K. Yamaguchi:
  Chain Closure: A Problem in Molecular CAD. 497-502
  
• Patrick C. McGeer, Steven Trimberger, Erik Carlson, Dave Hightower, Ulrich Lauther, Alberto L. Sangiovanni-Vincentelli:
  DA Algorithms in Non-EDA Applications: How Universal Are Our Techniques? (Panel). 503
  

Fault Simulation and Diagnosis

• Irith Pomeranz, Sudhakar M. Reddy:
  On Improving Fault Diagnosis for Synchronous Sequential Circuits. 504-509
  
• Takaharu Nagumo, Masahiko Nagai, Takao Nishida, Masayuki Miyoshi, Shunsuke Miyamoto:
  VFSIM: Vectorized Fault Simulator Using a Reduction Technique Excluding Temporarily Unobservable Faults. 510-515
  
• Keerthi Heragu, Michael L. Bushnell, Vishwani D. Agrawal:
  An Efficient Path Delay Fault Coverage Estimator. 516-521
  
• Manfred Henftling, Hannes C. Wittmann, Kurt Antreich:
  Path Hashing to Accelerate Delay Fault Simulation. 522-526
  

World Class Electronic Design Methodologies I

• Kenneth A. Radtke:
  The AT&T 5ESS Hardware Design Environment: A Large System's Hardware design Process. 527-531
  

New Ideas in High-level Synthesis

• Albert E. Casavant:
  MIST - A Design Aid for Programmable Pipelined Processors. 532-536
  
• Hong Shin Jun, Sun Young Hwang:
  Automatic Synthesis of Pipeline Structures with Variable Data Initiation Intervals. 537-541
  
• Yaw Fann, Minjoong Rim, Rajiv Jain:
  Global Scheduling for High-Level Synthesis Applications. 542-546
  
• Sanjiv Narayan, Daniel Gajski:
  Protocol Generation for Communication Channels. 547-551
  
• Ramesh Karri, Alex Orailoglu:
  Area-Efficient Fault Detection During Self-Recovering Microarchitecture Synthesis. 552-556
  
• Lawrence F. Arnstein, Donald E. Thomas:
  The Attributed-Behavior Abstraction and Synthesis Tools. 557-561
  

Panel

• Nikil D. Dutt, David Agnew, Raul Camposano, Antun Domic, Manfred Wiesel, Hiroto Yasuura:
  Design Reuse: Fact or Fiction? (Panel). 562
  

Electrical and Thermal Analysis

• Andrew B. Kahng, Sudhakar Muddu:
  Delay Analysis of VLSI Interconnections Using the Diffusion Equation Model. 563-569
  
• Vladimir Koval, Igor W. Farmaga, Andrzej J. Strojwas, Stephen W. Director:
  MONSTR: A Complete Thermal Simulator of Electronic Systems. 570-575
  
• Florentin Dartu, Noel Menezes, Jessica Qian, Lawrence T. Pillage:
  A Gate-Delay Model for high-Speed CMOS Circuits. 576-580
  
• Chung-Jung Chen, Wu-Shiung Feng:
  Transient Sensitivity Computation of MOSFET Circuits Using Iterated Timing Analysis and Selective-Tracing Waveform Eelaxation. 581-585
  

World Class Design Methodologies II

• Thomas F. Fox:
  The Design of High-Performance Microprocessors at Digital. 586-591
  
• Tadahiko Nishimukai:
  Hitachi-PA/50, SH Series Microcontroller. 592-593
  
• Matthias Schöbinger, Tobias G. Noll:
  Low Power CMOS Design Strategies. 594-595
  

Formal Verification of Systems

• Derek L. Beatty, Randal E. Bryant:
  Formally Verifying a Microprocessor Using a Simulation Methodology. 596-602
  
• Vishal Bhagwati, Srinivas Devadas:
  Automatic Verification of Pipelined Microprocessors. 603-608
  
• Eric Verlind, Tilman Kolks, Gjalt G. de Jong, Bill Lin, Hugo De Man:
  A Time Abstraction Method for Efficient Verification of Communicating Systems. 609-614
  
• A. S. Krishnakumar, Kwang-Ting Cheng:
  On the Computation of the Set of Reachable States of Hybrid Models. 615-621
  

Interconnect Analysis

• Tuyen V. Nguyen:
  Efficient Simulation of Lossy and Dispersive Transmission Lines. 622-627
  
• Monjurul Haque, Ali El-Zein, Salim Chowdhury:
  A New Time-Domain Macromodel for Transient Simulation of Uniform/Nonuniform Multiconductor Transmission-Line Interconnections. 628-633
  
• Luis Miguel Silveira, Ibrahim M. Elfadel, Jacob White, Moni Chilukuri, Kenneth S. Kundert:
  An Efficient Approach to Transmission Line Simulation Using Measured or Tabulated S-parameter Data. 634-639
  
• Rohini Gupta, Lawrence T. Pillage:
  OTTER: Optimal Termination of Transmission Lines Excluding Radiation. 640-645
  

Circuit Partitioning

• Bernhard M. Riess, Konrad Doll, Frank M. Johannes:
  Partitioning Very Large Circuits Using Analytical Placement Techniques. 646-651
  
• Charles J. Alpert, Andrew B. Kahng:
  Multi-Way Partitioning Via Spacefilling curves and Dynamic Programming. 652-657
  
• Lung-Tien Liu, Minshine Shih, Chung-Kuan Cheng:
  Data Flow Partitioning for Clock Period and Latency Minimization. 658-663
  
• Thang Nguyen Bui, Byung Ro Moon:
  A Fast and Stable Hybrid Genetic Algorithm for the Ratio-Cut Partitioning Problem on Hypergraphs. 664-669
  
• Jason Cong, Zheng Li, Rajive Bagrodia:
  Acyclic Multi-Way Partitioning of Boolean Networks. 670-675
  

Panel

• Kella Knack, Gordan Hyland, Jim Jasmin, John Frediani, Tom Reiner, Steven Trimberger, Gabriele Saucier:
  Design Automation Tools for FPGA Design (Panel). 676
  

Sequential Synthesis

• Huey-Yih Wang, Robert K. Brayton:
  Permissible Observability Relations in FSM Networks. 677-683
  
• Timothy Kam, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
  A Fully Implicit Algorithm for Exact State Minimization. 684-690
  
• Shankar Krishnamoorthy, Frederic Mailhot:
  Boolean Matching of Sequential Elements. 691-697
  

New Techniques in Test Generation

• Elizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, Thomas M. Niermann:
  Sequential Circuit Test Generation in a Genetic Algorithm Framework. 698-704
  
• João P. Marques Silva, Karem A. Sakallah:
  Dynamic Search-Space Pruning Techniques in Path Sensitization. 705-711
  
• Bapiraju Vinnakota, Jason Andrews:
  Functional Test Generation for FSMs by Fault Extraction. 712-715
  
• Steven Parkes, Prithviraj Banerjee, Janak H. Patel:
  ProperHITEC: A Portable, Parallel, Object-Oriented Approach to Sequential Test Generation. 717-721
  

Discrete Simulation

• Peter Dahlgren, Peter Lidén:
  Modeling of Intermediate Node States in switch-Level Networks. 722-727
  
• Michael G. Xakellis, Farid N. Najm:
  Statistical Estimation of the Switching Activity in Digital Circuits. 728-733
  
• Bhanu Kapoor:
  Improving the Accuracy of Circuit Activity Measurement. 734-739