ICCD 1997:
Austin,
Texas,
USA
Proceedings 1997 International Conference on Computer Design:
VLSI in Computers & Processors,
ICCD '97,
Austin,
Texas,
USA,
October 12-15,
1997. IEEE Computer Society Press,
1997,
ISBN 0-8186-8026-X
Session 1.1:
Keynote Speech
- David A. Patterson, Krste Asanovic, Aaron B. Brown, Richard Fromm, Jason Golbus, Benjamin Gribstad, Kimberly Keeton, Christoforos E. Kozyrakis, David Martin, Stylianos Perissakis, Randi Thomas, Noah Treuhaft, Katherine A. Yelick:
Intelligent RAM (IRAM): The Industrial Setting, Applications and Architectures.
2-7
Session 1.2:
CAD Plenary
- Ronald A. Rohrer:
A Brief History of the Future of Semiconductor Electronic Design Automation.
10-11
Session 1.3.1:
Special Session:
Industrial Application of Formal Verification
(There is no Session 1.3.2)
Session 1.3.3:
Simulation and Power Estimation
Session 1.3.4:
Branch Prediction
Session 1.4.1:
New Techniques for Gate-Sizing and Retiming
Session 1.4.2:
Circuit Modeling
Session 1.4.3:
Novel Architectures
Short Papers
Session 1.4.4:
Low Power Architectures
Session 1.5.1:
Timing Optimization for Deep Submicron Technology
Session 1.5.2:
Special Session:
The G4 S/390 Microprocessor
Session 1.5.3:
Multiprocessor Communication
- Robert Castañeda, Xiaodong Zhang, James M. Hoover Jr.:
A Comparative Evaluation of Hierarchical Network Architecture of the HP-Convex Exemplar.
258-266
- Hitoshi Oi, N. Ranganathan:
Effect of Message Length and Processor Speed on the Performance of the Bidirectional Ring-Based Multiprocessor.
267-272
- Michael Kozuch, Wayne Wolf, Andrew Wolfe:
An Approach to Network Caching for Multimedia Objects.
273-278
- W. K. Luk, Y. Katayama, Wei Hwang, Matthew R. Wordeman, T. Kirihata, Akashi Satoh, Seiji Munetoh, H. Wong, B. El-Kareh, P. Xiao, Rajiv V. Joshi:
Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip.
279-285
Session 1.5.4:
Asynchronous Architectures
Session 1.6.1:
Panel:
The War of the Roses:
Designers versus Tool Developers
Session 1.6.2:
Panel:
If Software is King for Systems-on-Silicon,
What's New in Compilers?
Session 2.1:
Design and Test Plenary
Session 2.2.1:
Binary Decision Diagrams
- Somesh Jha, Yuan Lu, Marius Minea, Edmund M. Clarke:
Equivalence Checking Using Abstract BDDs.
332-337
- Christoph Meinel, Anna Slobodová:
Speeding up Variable Reordering of OBDDs.
338-343
- Rajeev K. Ranjan, Wilsin Gosti, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Dynamic Reordering in a Breadth-First Manipulation Based BDD Package: Challenges and Solutions.
344-351
- Zhongcheng Li, Yuhong Zhao, Yinghua Min, Robert K. Brayton:
Timed Binary Decision Diagrams.
352-357
Session 2.2.2:
Advanced Test Topics
Session 2.2.3:
Embedded Software and Systems
Session 2.2.4:
Low Power Issues
Session 2.3.1:
Formal Verification Methods
Session 2.3.2:
Mixed Signal Design and Test
Session 2.3.3:
FPGA Design
Session 2.3.4:
Cache Technology I
Session 2.4.1:
Embedded Tutorial
- Kenneth L. Shepard:
Practical Issues of Interconnect Analysis in Deep Submicron Integrated Circuits.
532-541
Session 2.4.2:
Fault Diagnosis
Session 2.4.3:
Special Session:
Low Power Design Issues
Session 2.4.4:
Cache Technology II
Session 3.1:
Architecture & Algorithm Plenary
Session 3.2.1:
Layout Partitioning and Synthesis
Session 3.2.2:
Design for Testabiliy & Test Synthesis
Session 3.2.3:
Embedded Tutorial
Session 3.2.4:
Arithmetics
Session 3.3.1:
Asynchronous Design
Session 3.3.2:
Special Session:
Interconnect Modeling & Repeater Methodologies
Session 3.3.3:
Finite-State Machine and High-Level Synthesis
Copyright © Fri Mar 12 17:13:15 2010
by Michael Ley (ley@uni-trier.de)
