IMS 2000: Cambridge, MA, USA

@proceedings{DBLP:conf/ims/2000,
  editor    = {Frederic T. Chong and
               Christoforos E. Kozyrakis and
               Mark Oskin},
  title     = {Intelligent Memory Systems, Second International Workshop, IMS
               2000, Cambridge, MA, USA, November 12, 2000, Revised Papers},
  booktitle = {Intelligent Memory Systems},
  publisher = {Springer},
  series    = {Lecture Notes in Computer Science},
  volume    = {2107},
  year      = {2001},
  isbn      = {3-540-42328-1},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

Memory Technology

• Junji Ogawa, Mark Horowitz:
  A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro. 1-14
  
• Hiroshi Nakamura, Masaaki Kondo, Taisuke Boku:
  Software Controlled Reconfigurable On-Chip Memory for High Performance Computing. 15-32
  

Processor and Memory Architecture

• Robert Cooksey, Dennis Colarelli, Dirk Grunwald:
  Content-Based Prefetching: Initial Results. 33-55
  
• Lixin Zhang, Venkata K. Pingali, Bharat Chandramouli, John B. Carter:
  Memory System Support for Dynamic Cache Line Assembly. 56-70
  
• Yan Solihin, Jaejin Lee, Josep Torrellas:
  Adaptively Mapping Code in an Intelligent Memory Architecture. 71-84
  

Applications and Operating Systems

• Richard C. Murphy, Peter M. Kogge, Arun Rodrigues:
  The Characterization of Data Intensive Memory Workloads on Distributed PIM Systems. 85-103
  
• Mary W. Hall, Craig S. Steele:
  Memory Management in a PIM-Based Architecture. 104-121
  

Compiler Technology

• David Judd, Katherine A. Yelick, Christoforos E. Kozyrakis, David Martin, David A. Patterson:
  Exploiting On-Chip Memory Bandwidth in the VIRAM Compiler. 122-134
  
• Csaba Andras Moritz, Matthew Frank, Saman P. Amarasinghe:
  FlexCache: A Framework for Flexible Compiler Generated Data Caching. 135-146
  

Poster Session

• Peter Grun, Nikil D. Dutt, Alexandru Nicolau:
  Aggressive Memory-Aware Compilation. 147-151
  
• Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas:
  Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips. 152-159
  
• Tsung-Chuan Huang, Slo-Li Chu:
  SAGE: A New Analysis and Optimization System for FlexRAM Architecture. 160-168
  
• Koji Inoue, Koji Kai, Kazuaki Murakami:
  Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems. 169-178
  
• Jeff La Coss:
  The DIVA Emulator: Accelerating Architecture Studies for PIM-Based Systems. 179-182
  
• Dan Nicolaescu, Xiaomei Ji, Alexander V. Veidenbaum, Alexandru Nicolau, Rajesh K. Gupta:
  Compiler-Directed Cache Line Size Adaptivity. 183-187
  
• Workshop Notes. 188-192