 | 2009 |
|---|
| 38 |       | Alexandre Schmid,
Sanjay Goel,
Wei Wang,
Valeriu Beiu,
Sandro Carrara:
Nano-Net - 4th International ICST Conference, Nano-Net 2009, Lucerne, Switzerland, October 18-20, 2009. Proceedings
Springer 2009 |
| 37 | | Valeriu Beiu,
Basheer A. M. Madappuram,
Peter M. Kelly,
Liam McDaid:
On Two-Layer Hierarchical Networks How Does the Brain Do This?
NanoNet 2009: 231-241 |
| 36 | | Peter M. Kelly,
Fergal Tuffy,
Valeriu Beiu,
Liam McDaid:
Reduced Interconnects in Neural Networks Using a Time Multiplexed Architecture Based on Quantum Devices.
NanoNet 2009: 242-250 |
| 35 | | Valeriu Beiu,
Walid Ibrahim,
Rafic Z. Makki:
On Wires Holding a Handful of Electrons.
NanoNet 2009: 259-269 |
| 34 | | Walid Ibrahim,
Valeriu Beiu:
A Bayesian-Based EDA Tool for Nano-circuits Reliability Calculations.
NanoNet 2009: 276-284 |
| 2008 |
|---|
| 33 | | Valeriu Beiu,
Walid Ibrahim:
Does the brain really outperform Rent's rule?
ISCAS 2008: 640-643 |
| 2007 |
|---|
| 32 | | Walid Ibrahim,
Valeriu Beiu:
Long Live Small Fan-in Majority Gates Their Reign Looks Like Coming!
ASAP 2007: 278-283 |
| 31 | | Valeriu Beiu:
Grand Challenges of Nanoelectronics and Possible Architectural Solutions: What Do Shannon, von Neumann, Kolmogorov, and Feynman Have to do with Moore.
ISMVL 2007 |
| 30 | | Valeriu Beiu,
Walid Ibrahim,
Sanja Lazarova-Molnar:
What von Neumann Did Not Say About Multiplexing Beyond Gate Failures - The Gory Details.
IWANN 2007: 487-496 |
| 2006 |
|---|
| 29 | | Valeriu Beiu,
Jabulani Nyathi,
Snorre Aunet,
Mawahib H. Sulieman:
Femto Joule Switching for Nano Electronics.
AICCSA 2006: 415-423 |
| 28 | | Mawahib H. Sulieman,
Valeriu Beiu:
Multiplexing Schemes in Single-Electron Technology.
AICCSA 2006: 424-428 |
| 27 | | Valeriu Beiu,
Walid Ibrahim,
Y. A. Alkhawwar,
Mawahib H. Sulieman:
Gate Failures Effectively Shape Multiplexing.
DFT 2006: 29-40 |
| 2005 |
|---|
| 26 | | Valeriu Beiu,
Snorre Aunet,
Jabulani Nyathi,
Ray Robert Rydberg III,
Asbjørn Djupdal:
On the Advantages of Serial Architectures for Low-Power Reliable Computations.
ASAP 2005: 276-281 |
| 25 | | Valeriu Beiu,
Artur Zawadski,
Razvan Andonie,
Snorre Aunet:
Using Kolmogorov Inspired Gates for Low Power Nanoelectronics.
IWANN 2005: 438-445 |
| 24 | | Valeriu Beiu,
Asbjørn Djupdal,
Snorre Aunet:
Ultra Low-Power Neural Inspired Addition: When Serial Might Outperform Parallel Architectures.
IWANN 2005: 486-493 |
| 2004 |
|---|
| 23 | | Valeriu Beiu:
A Novel Highly Reliable Low-Power Nano Architecture When von Neumann Augments.
ASAP 2004: 167-177 |
| 22 |  | David J. Betowski,
Daniel Dwyer,
Valeriu Beiu:
A Novel Segmented Parabolic Sine Approximation for Direct Digital Frequency Synthesizers.
ESA/VLSI 2004: 523-529 |
| 21 | | Valeriu Beiu,
Mawahib H. Sulieman:
Optimal Practical Perceptron Addition Application to Single Electron Technology.
ESA/VLSI 2004: 541-550 |
| 20 | | Mawahib H. Sulieman,
Valeriu Beiu:
Characterization of a 16-bit threshold logic single-electron technology adder.
ISCAS (3) 2004: 681-684 |
| 2003 |
|---|
| 19 | | Valeriu Beiu,
Maria J. Avedillo,
José M. Quintana:
Review of Capacitive Threshold Gate Implementations.
ICANN 2003: 737-744 |
| 18 | | Valeriu Beiu:
Constructive Threshold Logic Addition A Synopsis of the Last Decade.
ICANN 2003: 745-752 |
| 17 | | Suryanarayana Tatapudi,
Valeriu Beiu:
Split-Precharge Differential Noise-Immune Threshold Logic Gate (SPD-NTL).
IWANN (2) 2003: 49-56 |
| 16 | | Razvan Andonie,
Lucian Sasu,
Valeriu Beiu:
A Modified Fuzzy ARTMAP Architecture for Incremental Learning Function Approximation.
Neural Networks and Computational Intelligence 2003: 124-129 |
| 15 | | Valeriu Beiu,
José M. Quintana,
Maria J. Avedillo:
Review of Differential Threshold Gate Implementations.
Neural Networks and Computational Intelligence 2003: 44-49 |
| 14 | | Valeriu Beiu:
On Existential and Constructive Neural Complexity Results.
Neural Networks and Computational Intelligence 2003: 63-72 |
| 1999 |
|---|
| 13 | | Valeriu Beiu:
Neural Addition and Fibonacci Numbers.
IWANN (2) 1999: 198-207 |
| 12 | | Valeriu Beiu,
Sorin Draghici,
Thierry de Pauw:
A Constructive Approach to Calculating Lower Entropy Bounds.
Neural Processing Letters 9(1): 1-12 (1999) |
| 1998 |
|---|
| 11 | | Valeriu Beiu:
2D Neural Hardware versus 3D Biological Ones.
NC 1998: 36-42 |
| 10 | | Valeriu Beiu:
On Kolmogorov's Superpositions and Boolean Functions.
SBRN 1998: 55-60 |
| 9 | | Valeriu Beiu,
Hanna E. Makaruk:
Deeper Sparsely Nets can be Optimal.
Neural Processing Letters 8(3): 201-210 (1998) |
| 8 | | Valeriu Beiu:
On the circuit and VLSI complexity of threshold gate COMPARISON.
Neurocomputing 19(1-3): 77-98 (1998) |
| 1997 |
|---|
| 7 | | Valeriu Beiu:
Enhanced lower entropy bounds with application to constructive learning.
EUROMICRO 1997: 541-548 |
| 6 | | Valeriu Beiu,
Thierry de Pauw:
Tight Bounds on the Size of Neural Networks for Classification Problems.
IWANN 1997: 743-752 |
| 5 | | Valeriu Beiu,
Sorin Draghici,
Hanna E. Makaruk:
On limited fan-in optimal neural networks.
SBRN 1997: 19-30 |
| 1996 |
|---|
| 4 | | Valeriu Beiu,
John G. Taylor:
On the Circuit Complexity of Sigmoid Feedforward Neural Networks.
Neural Networks 9(7): 1155-1171 (1996) |
| 1995 |
|---|
| 3 | | Valeriu Beiu,
John G. Taylor:
Optimal Mapping of Neural Networks onto FPGA's - A New Constructive Algorithm -.
IWANN 1995: 822-829 |
| 1994 |
|---|
| 2 | | Valeriu Beiu,
J. A. Peperstraete,
Joos Vandewalle,
Rudy Lauwereins:
Closse Approximations of Sigmoid Functions by Sum of Step for VLSI Implementation of Neural Networks.
Sci. Ann. Cuza Univ. 3: 5-34 (1994) |
| 1988 |
|---|
| 1 | | Valeriu Beiu:
VLSI arrays implementing parallel line-drawing algorithms.
Parcella 1988: 241-247 |
