 | 2009 |
|---|
| 153 |       | Jürgen Becker,
Roger Woods,
Peter M. Athanas,
Fearghal Morgan:
Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings
Springer 2009 |
| 152 | | Krzysztof Kepa,
Fearghal Morgan,
Krzysztof Kosciuszkiewicz,
Lars Braun,
Michael Hübner,
Jürgen Becker:
FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing.
ARC 2009: 62-73 |
| 151 | | Oliver Sander,
Benjamin Glas,
Christoph Roth,
Jürgen Becker,
Klaus D. Müller-Glaser:
Priority-based packet communication on a bus-shaped structure for FPGA-systems.
DATE 2009: 178-183 |
| 150 |  | Jürgen Becker:
Adaptive Multicore Systems-on-Chip (MSoC) - Design and Computing in the Nano Era.
ERSA 2009: 55-66 |
| 149 | | Benjamin Glas,
Alexander Klimm,
Klaus D. Müller-Glaser,
Jürgen Becker:
Configuration Measurement for FPGA-based Trusted Platforms.
IEEE International Workshop on Rapid System Prototyping 2009: 123-129 |
| 148 | | Oliver Sander,
Benjamin Glas,
Christoph Roth,
Jürgen Becker,
Klaus D. Müller-Glaser:
Testing of an FPGA Based C2X-Communication Prototype with a Model Based Traffic Generation.
IEEE International Workshop on Rapid System Prototyping 2009: 68-71 |
| 147 | | Alexander Klimm,
Oliver Sander,
Jürgen Becker:
A MicroBlaze specific co-processor for real-time hyperelliptic curve cryptography on Xilinx FPGAs.
IPDPS 2009: 1-8 |
| 146 | | Oliver Sander,
Christoph Roth,
Vitali Stuckert,
Jürgen Becker:
System concept for an FPGA based real-time capable automotive ECU simulation system.
SBCCI 2009 |
| 145 | | Katarina Paulsson,
Michael Hübner,
Jürgen Becker:
Dynamic power optimization by exploiting self-reconfiguration in Xilinx Spartan 3-based systems.
Microprocessors and Microsystems - Embedded Hardware Design 33(1): 46-52 (2009) |
| 2008 |
|---|
| 144 | | Oliver Sander,
Lars Braun,
Michael Hübner,
Jürgen Becker:
Data reallocation by exploiting FPGA configuration mechanisms.
ARC 2008: 308-313 |
| 143 | | Alexander Klimm,
Oliver Sander,
Jürgen Becker,
Sylvain Subileau:
A Hardware/Software Codesign of a Co-processor for Real-Time Hyperelliptic Curve Cryptography on a Spartan3 FPGA.
ARCS 2008: 188-201 |
| 142 | | Antonio Deledda,
Claudio Mucci,
Arseni Vitkovski,
Philippe Bonnot,
Arnaud Grasset,
P. Millet,
Matthias Kühnle,
Florian Ries,
Michael Hübner,
Jürgen Becker,
Massimo Coppola,
Lorenzo Pieralisi,
Riccardo Locatelli,
Giuseppe Maruccia,
Fabio Campi,
Tommaso DeMarco:
Design of a HW/SW Communication Infrastructure for a Heterogeneous Reconfigurable Processor.
DATE 2008: 1352-1357 |
| 141 | | Katarina Paulsson,
Michael Hübner,
Jürgen Becker:
Cost-and Power Optimized FPGA based System Integration: Methodologies and Integration of a Low-Power Capacity-based Measurement Application on Xilinx FPGAs.
DATE 2008: 50-55 |
| 140 | | Benjamin Glas,
Alexander Klimm,
Oliver Sander,
Klaus D. Müller-Glaser,
Jürgen Becker:
A System Architecture for Reconfigurable Trusted Platforms.
DATE 2008: 541-544 |
| 139 | | Ralf König,
Timo Stripf,
Jürgen Becker:
A Novel Recursive Algorithm for Bit-Efficient Realization of Arbitrary Length Inverse Modified Cosine Transforms.
DATE 2008: 604-609 |
| 138 | | Jürgen Becker,
Michael Hübner,
Robert Esser,
Andreas Herkersdorf,
Walter Stechele,
Vera Lauer:
Design Flows, Communication Based Design and Architectures in Automotive Electronic Systems.
DATE 2008 |
| 137 | | Carlos Morra,
João Bispo,
João M. P. Cardoso,
Jürgen Becker:
Combining Rewriting-Logic, Architecture Generation, and Simulation to Exploit Coarse-Grained Reconfigurable Architectures.
FCCM 2008: 320-321 |
| 136 | | Josef Angermeier,
Mateusz Majer,
Jürgen Teich,
Lars Braun,
T. Schwalb,
Philipp Graf,
Michael Hübner,
Jürgen Becker,
Enno Lübbers,
Marco Platzner,
Christopher Claus,
Walter Stechele,
Andreas Herkersdorf,
Markus Rullmann,
Renate Merker:
Fine grain reconfigurable architectures.
FPL 2008: 348 |
| 135 | | Sven Eisenhardt,
Thomas Schweizer,
Julio A. de Oliveira Filho,
Tobias Oppold,
Wolfgang Rosenstiel,
Alexander Thomas,
Jürgen Becker,
Frank Hannig,
Dmitrij Kissler,
Hritam Dutta,
Jürgen Teich,
Heiko Hinkelmann,
Peter Zipf,
Manfred Glesner:
Coarse-grained reconfiguration.
FPL 2008: 349 |
| 134 | | Diana Göhringer,
Michael Hübner,
Thomas Perschke,
Jürgen Becker:
New dimensions for multiprocessor architectures: Ondemand heterogeneity, infrastructure and performance through reconfigurability - the RAMPSoC approach.
FPL 2008: 495-498 |
| 133 | | Christopher Claus,
Bin Zhang,
Walter Stechele,
Lars Braun,
Michael Hübner,
Jürgen Becker:
A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput.
FPL 2008: 535-538 |
| 132 | | Lars Braun,
Katarina Paulsson,
Herrmann Krömer,
Michael Hübner,
Jürgen Becker:
Data path driven waveform-like reconfiguration.
FPL 2008: 607-610 |
| 131 | | Katarina Paulsson,
Michael Hübner,
Jürgen Becker:
Exploitation of dynamic and partial hardware reconfiguration for on-line power/performance optimization.
FPL 2008: 699-700 |
| 130 | | Benjamin Glas,
Alexander Klimm,
David Schwab,
Klaus D. Müller-Glaser,
Jürgen Becker:
A Prototype of Trusted Platform Functionality on Reconfigurable Hardware for Bitstream Updates.
IEEE International Workshop on Rapid System Prototyping 2008: 135-141 |
| 129 | | Benjamin Glas,
Alexander Klimm,
Oliver Sander,
Klaus D. Müller-Glaser,
Jürgen Becker:
A self adaptive interfacing concept for consumer device integration into automotive entities.
IPDPS 2008: 1-6 |
| 128 | | Michael Hübner,
Lars Braun,
Diana Göhringer,
Jürgen Becker:
Run-time reconfigurable adaptive multilayer network-on-chip for FPGA-based systems.
IPDPS 2008: 1-6 |
| 127 | | Christian Schuck,
Matthias Kühnle,
Michael Hübner,
Jürgen Becker:
A framework for dynamic 2D placement on FPGAs.
IPDPS 2008: 1-7 |
| 126 | | Alexander Klimm,
Lars Braun,
Jürgen Becker:
An adaptive and scalable multiprocessor system For Xilinx FPGAs using minimal sized processor cores.
IPDPS 2008: 1-7 |
| 125 | | Diana Göhringer,
Michael Hübner,
Volker Schatz,
Jürgen Becker:
Runtime adaptive multi-processor system-on-chip: RAMPSoC.
IPDPS 2008: 1-7 |
| 124 | | Jürgen Becker:
Adaptive Reliable Chips - Reconfigurable Computing in the Nano Era.
ISVLSI 2008: 1-2 |
| 123 | | Katarina Paulsson,
Ulrich Viereck,
Michael Hübner,
Jürgen Becker:
Exploitation of the External JTAG Interface for Internally Controlled Configuration Readback and Self-Reconfiguration of Spartan 3 FPGAs.
ISVLSI 2008: 304-309 |
| 122 | | Sunil Shukla,
Neil W. Bergmann,
Jürgen Becker:
A Web Server Based Edge Detector Implementation in FPGA.
ISVLSI 2008: 441-446 |
| 121 | | Juanjo Noguera,
Robert Esser,
Katarina Paulsson,
Michael Hübner,
Jürgen Becker:
Towards Novel Approaches in Design Automation for FPGA Power Optimization.
PATMOS 2008: 419-428 |
| 120 | | Carlos Morra,
João M. P. Cardoso,
João Bispo,
Jürgen Becker:
Retargeting, Evaluating, and Generating Reconfigurable Array-Based Architectures.
SASP 2008: 34-41 |
| 119 | | Matthias Kühnle,
Michael Hübner,
Jürgen Becker,
Antonio Deledda,
Claudio Mucci,
Florian Ries,
Marcello Coppola,
Lorenzo Pieralisi,
Riccardo Locatelli,
Giuseppe Maruccia,
Tommaso DeMarco,
Fabio Campi:
An Interconnect Strategy for a Heterogeneous, Reconfigurable SoC.
IEEE Design & Test of Computers 25(5): 442-451 (2008) |
| 2007 |
|---|
| 118 | | Katarina Paulsson,
Michael Hübner,
Günther Auer,
Michael Dreschmann,
Jürgen Becker:
Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAs.
FPL 2007: 351-356 |
| 117 | | Christian Schuck,
Stefan Lamparth,
Jürgen Becker:
artNoC - A Novel Multi-Functional Router Architecture for Organic Computing.
FPL 2007: 371-376 |
| 116 | | Florian Thoma,
Matthias Kühnle,
Philippe Bonnot,
Elena Moscu Panainte,
Koen Bertels,
Sebastian Goller,
Axel Schneider,
Stéphane Guyetant,
Eberhard Schüler,
Klaus D. Müller-Glaser,
Jürgen Becker:
MORPHEUS: Heterogeneous Reconfigurable Computing.
FPL 2007: 409-414 |
| 115 | | Katarina Paulsson,
Michael Hübner,
Jürgen Becker,
Jean-Marc Philippe,
Christian Gamrat:
On-line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations within the ÆTHER Project.
FPL 2007: 415-422 |
| 114 | | Mahendra Kumar Angamuthu Ganesan,
Sundeep Singh,
Frank May,
Jürgen Becker:
H.264 Decoder at HD Resolution on a Coarse Grain Dynamically Reconfigurable Architecture.
FPL 2007: 467-471 |
| 113 | | Lars Braun,
Michael Hübner,
Jürgen Becker,
Thomas Perschke,
Volker Schatz,
Stefan Bach:
Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications.
FPL 2007: 688-691 |
| 112 | | Philipp Graf,
Michael Hübner,
Klaus D. Müller-Glaser,
Jürgen Becker:
A Graphical Model-Level Debugger for Heterogenous Reconfigurable Architectures.
FPL 2007: 722-725 |
| 111 | | Alisson Vasconcelos De Brito,
Matthias Kühnle,
Elmar U. K. Melcher,
Jürgen Becker:
A General Purpose Partially Reconfigurable Processor Simulator (PReProS).
IPDPS 2007: 1-7 |
| 110 | | Sunil Shukla,
Neil W. Bergmann,
Jürgen Becker:
QUKU: A FPGA Based Flexible Coarse Grain Architecture Design Paradigm using Process Networks.
IPDPS 2007: 1-7 |
| 109 | | Thilo Pionteck,
Carsten Albrecht,
Roman Koch,
Erik Maehle,
Michael Hübner,
Jürgen Becker:
Communication Architectures for Dynamically Reconfigurable FPGA Designs.
IPDPS 2007: 1-8 |
| 108 | | Maik Boden,
Thomas Fiebig,
Torsten Meibner,
Steffen Rülke,
Jürgen Becker:
High-Level Synthesis of HW Tasks Targeting Run-Time Reconfigurable FPGAs.
IPDPS 2007: 1-8 |
| 107 | | Carlos Morra,
João M. P. Cardoso,
Jürgen Becker:
Using Rewriting Logic to Match Patterns of Instructions from a Compiler Intermediate Form to Coarse-Grained Processing Elements.
IPDPS 2007: 1-8 |
| 106 | | Alisson Vasconcelos De Brito,
Matthias Kühnle,
Michael Hübner,
Jürgen Becker,
Elmar U. K. Melcher:
Modelling and Simulation of Dynamic and Partially Reconfigurable Systems using SystemC.
ISVLSI 2007: 35-40 |
| 105 | | Michael Hübner,
Lars Braun,
Jürgen Becker,
Christopher Claus,
Walter Stechele:
Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs.
ISVLSI 2007: 41-46 |
| 104 | | Katarina Paulsson,
Michael Hübner,
Salih Bayar,
Jürgen Becker:
Exploitation of Run-Time Partial Reconfiguration for Dynamic Power Management in Xilinx Spartan III-based Systems.
ReCoSoC 2007: 1-6 |
| 103 | | Jürgen Becker,
Adam Donlin,
Michael Hübner:
New tool support and architectures in adaptive reconfigurable computing.
VLSI-SoC 2007: 134-139 |
| 102 | | Sebastian Wieskotten,
Stefanie Heinke,
Peter Wabel,
Ulrich Moissl,
Jürgen Becker,
Matthias Pirlich,
Michael Keymling,
Rolf Isermann:
Modell-basierte Erkennung von Mangelernährung mittels Bioimpedanzspektroskopie (Model-based Identification of Malnutrition via Bioimpedance Spectroscopy).
Automatisierungstechnik 55(10): 531-538 (2007) |
| 101 | | Michael Ullmann,
Wansheng Jin,
Jürgen Becker:
Hardware Support for QoS-based Function Allocation in Reconfigurable Systems
CoRR abs/0710.4850: (2007) |
| 100 | | Alexander Thomas,
Jürgen Becker:
New Adaptive Multi-grained Hardware Architecture for Processing of Dynamic Function Patterns (Neue adaptive multi-granulare Hardwarearchitektur).
it - Information Technology 49(3): 165- (2007) |
| 2006 |
|---|
| 99 | | Claudionor José Nunes Coelho Jr.,
Ricardo P. Jacobi,
Jürgen Becker:
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2006, Ouro Preto, MG, Brazil, August 28 - September 1, 2006
ACM 2006 |
| 98 | | Wolfgang Karl,
Jürgen Becker,
Karl-Erwin Großpietsch,
Christian Hochberger,
Erik Maehle:
ARCS 2006 - 19th International Conference on Architecture of Computing Systems, Workshops Proceedings, March 16, 2006, Frankfurt am Main, Germany
GI 2006 |
| 97 | | Peter M. Athanas,
Jürgen Becker,
Gordon J. Brebner,
Jürgen Teich:
Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006
Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany 2006 |
| 96 | | Katarina Paulsson,
Michael Hübner,
Jürgen Becker:
Strategies to On- Line Failure Recovery in Self- Adaptive Systems based on Dynamic and Partial Reconfiguration.
AHS 2006: 288-291 |
| 95 | | Sunil Shukla,
Neil W. Bergmann,
Jürgen Becker:
QUKU: A Fast Run Time Reconfigurable Platform for Image Edge Detection.
ARC 2006: 93-98 |
| 94 | | Jürgen Becker,
Kurt Brändle,
Uwe Brinkschulte,
Jörg Henkel,
Wolfgang Karl,
Thorsten Köster,
Michael Wenz,
Heinz Wörn:
Digital On-Demand Computing Organism for Real-Time Systems.
ARCS Workshops 2006: 230-245 |
| 93 | | Jürgen Becker,
Jürgen Teich,
Gordon J. Brebner,
Peter M. Athanas:
06141 Abstracts Collection -- Dynamically Reconfigurable Architectures.
Dynamically Reconfigurable Architectures 2006 |
| 92 | | Jürgen Becker,
Jürgen Teich,
Gordon J. Brebner,
Peter M. Athanas:
06141 Executive Summary -- Dynamically Reconfigurable Architectures.
Dynamically Reconfigurable Architectures 2006 |
| 91 | | Jürgen Becker,
Michael Hübner,
Katarina Paulsson:
Physical 2D Morphware and Power Reduction Methods for Everyone.
Dynamically Reconfigurable Architectures 2006 |
| 90 | | Sunil Shukla,
Neil W. Bergmann,
Jürgen Becker:
QUKU: A Coarse Grained Paradigm for FPGAs.
Dynamically Reconfigurable Architectures 2006 |
| 89 | | Carlos Morra,
M. Sackmann,
Sunil Shukla,
Jürgen Becker,
Reiner W. Hartenstein:
From Equation to VHDL: Using Rewriting Logic for Automated Function Generation.
FPL 2006: 1-4 |
| 88 | | Maik Boden,
Steffen Rülke,
Jürgen Becker:
A high-level target-precise model for designing reconfigurable HW tasks.
IPDPS 2006 |
| 87 | | Michael Hübner,
Christian Schuck,
Jürgen Becker:
Elementary block based 2-dimensional dynamic and partial reconfiguration for Virtex-II FPGAs.
IPDPS 2006 |
| 86 | | Sunil Shukla,
Neil W. Bergmann,
Jürgen Becker:
QUKU: A Two-Level Reconfigurable Architecture.
ISVLSI 2006: 109-116 |
| 85 | | Katarina Paulsson,
Michael Hübner,
Markus Jung,
Jürgen Becker:
Methods for Run-time Failure Recognition and Recovery in dynamic and partial Reconfigurable Systems Based on Xilinx Virtex-II Pro FPGAs.
ISVLSI 2006: 159-166 |
| 84 | | Pascal Benoit,
Lionel Torres,
Gilles Sassatelli,
Michel Robert,
Gaston Cambon,
Jürgen Becker:
Dynamic Hardware Multiplexing: Improving Adaptability with a Run Time Reconfiguration Manager.
ISVLSI 2006: 251-256 |
| 83 | | Michael Hübner,
Christian Schuck,
Matthias Kühnle,
Jürgen Becker:
New 2-Dimensional Partial Dynamic Reconfiguration Techniques for Real-time Adaptive Microelectronic Circuits.
ISVLSI 2006: 97-102 |
| 82 | | Carlos Morra,
M. Sackmann,
Jürgen Becker,
Reiner W. Hartenstein:
Using Rewriting Logic to Generate Different Implementations of Polynomial Approximations in Coarse-Grained Architectures.
ReCoSoC 2006: 46-51 |
| 81 | | Michael Hübner,
Jürgen Becker:
Exploiting dynamic and partial reconfiguration for FPGAs: toolflow, architecture and system integration.
SBCCI 2006: 1-4 |
| 80 | | Katarina Paulsson,
Michael Hübner,
Jürgen Becker:
On-line optimization of FPGA power-dissipation by exploiting run-time adaption of communication primitives.
SBCCI 2006: 173-178 |
| 79 | | Jürgen Becker,
Michael Hübner:
Run-time reconfigurabilility and other future trends.
SBCCI 2006: 9-11 |
| 2005 |
|---|
| 78 | | Laurence Tianruo Yang,
Hamid R. Arabnia,
Jürgen Becker,
Masaharu Imai,
Zoran A. Salcic:
Proceedings of The 2005 International Conference on Embedded Systems and Applications, ESA 2005, Las Vegas, Nevada, USA, June 27-30, 2005
CSREA Press 2005 |
| 77 | | Uwe Brinkschulte,
Jürgen Becker,
Dietmar Fey,
Christian Hochberger,
Thomas Martinetz,
Christian Müller-Schloer,
Hartmut Schmeck,
Theo Ungerer,
Rolf P. Würtz:
18th International Conference on Architecture of Computing Systems, Workshops, Innsbruck, Austria, March 2005
VDE Verlag 2005 |
| 76 | | Michael Hübner,
Katarina Paulsson,
Marcus Stitz,
Jürgen Becker:
Novel Seamless Design-Flow for Partial and Dynamic Reconfigurable Systems with Customized Communication Structures based on Xilinx Virtex-II FPGAs.
ARCS Workshops 2005: 39-44 |
| 75 | | Carlos Morra,
Jürgen Becker,
Mauricio Ayala-Rincón,
Reiner W. Hartenstein:
FELIX: Using Rewriting-Logic for Generating Functionally Equivalent Implementations.
FPL 2005: 25-30 |
| 74 | | Pascal Benoit,
Jürgen Becker,
Michel Robert,
Lionel Torres,
Gilles Sassatelli,
Gaston Cambon:
Run-Time Scheduling for Random Multi-Tasking in Reconfigurable Coprocessors.
FPL 2005: 703-706 |
| 73 | | Michael Ullmann,
Wansheng Jin,
Jürgen Becker:
Hardware Enhanced Function Allocation Management in Reconfigurable Systems.
IPDPS 2005 |
| 72 | | Michael Hübner,
Katarina Paulsson,
Jürgen Becker:
Parallel and Flexible Multiprocessor System-On-Chip for Adaptive Automotive Applications based on Xilinx MicroBlaze Soft-Cores.
IPDPS 2005 |
| 71 | | Alexander Thomas,
Jürgen Becker:
Multi-Grained Reconfigurable Datapath Structures for Online-Adaptive Reconfigurable Hardware Architectures.
ISVLSI 2005: 118-123 |
| 70 | | Carsten Bieser,
Klaus D. Müller-Glaser,
Jürgen Becker:
Hardware/Software Co-Training Lab: From VHDL Bit-Level Coding up to CASE-Tool Based System Modeling.
MSE 2005: 51-52 |
| 69 | | Jürgen Becker,
Michael Hübner,
Katarina Paulsson,
Alexander Thomas:
Dynamic Reconfiguration On-Demand: Real-time Adaptivity in Next Generation Microelectronics.
ReCoSoC 2005: 35-42 |
| 68 | | Jürgen Becker,
Alexander Thomas:
Scalable Processor Instruction Set Extension.
IEEE Design & Test of Computers 22(2): 136-148 (2005) |
| 67 | | Michael Ullmann,
Michael Hübner,
Jürgen Becker:
On-demand FPGA run-time system for flexible and dynamical reconfiguration.
IJES 1(3/4): 193-204 (2005) |
| 66 | | Michael Hübner,
Michael Ullmann,
Jürgen Becker:
Realtime configuration code decompression for dynamic FPGA self reconfiguration: evaluation and implementation.
IJES 1(3/4): 263-273 (2005) |
| 65 | | Jürgen Becker,
Kurt Brändle,
Michael Ullmann:
Rekonfigurierbare Hardware und intelligente Laufzeitsysteme für adaptives Rechnen.
it - Information Technology 47(4): 201-206 (2005) |
| 2004 |
|---|
| 64 | | Uwe Brinkschulte,
Jürgen Becker,
Dietmar Fey,
Karl-Erwin Großpietsch,
Christian Hochberger,
Erik Maehle,
Thomas A. Runkler:
ARCS 2004 - Organic and Pervasive Computing, Workshops Proceedings, March 26, 2004, Augsburg, Germany
GI 2004 |
| 63 | | Jürgen Becker,
Marco Platzner,
Serge Vernalde:
Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings
Springer 2004 |
| 62 | | Alexander Thomas,
Jürgen Becker:
Aufbau- und Strukturkonzepte einer adaptive multigranularen rekonfigurierbaren Hardwarearchitektur.
ARCS Workshops 2004: 165-174 |
| 61 | | Michael Ullmann,
Wansheng Jin,
Jürgen Becker:
Hardware Support for QoS-based Function Allocation in Reconfigurable Systems.
DATE 2004: 259-264 |
| 60 | | Michael Ullmann,
Wansheng Jin,
Jürgen Becker:
Hardware Support for QoS-based Function Allocation in Reconfigurable Systems.
DATE 2004: 259-264 |
| 59 | | Michael Hübner,
Michael Ullmann,
Lars Braun,
A. Klausmann,
Jürgen Becker:
Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems.
FPL 2004: 1037-1041 |
| 58 | | Alexander Thomas,
Jürgen Becker:
Dynamic Adaptive Runtime Routing Techniques in Multigrain Reconfigurable Hardware Architectures.
FPL 2004: 115-124 |
| 57 | | Michael Ullmann,
Michael Hübner,
Björn Grimm,
Jürgen Becker:
On-Demand FPGA Run-Time System for Dynamical Reconfiguration with Adaptive Priorities.
FPL 2004: 454-463 |
| 56 | | Uwe Brinkschulte,
Jürgen Becker,
Klaus Dorfmüller-Ulhaas,
Ralf König,
Sascha Uhrig,
Theo Ungerer:
CARUSO - Project Goals and Principal Approach.
GI Jahrestagung (2) 2004: 616-620 |
| 55 | | Michael Ullmann,
Michael Hübner,
Björn Grimm,
Jürgen Becker:
An FPGA Run-Time System for Dynamical On-Demand Reconfiguration.
IPDPS 2004 |
| 54 | | Uwe Brinkschulte,
Jürgen Becker,
Theo Ungerer:
CARUSO - An Approach Towards a Network of Low Power Autonomic Systems on Chips for Embedded Real-time Application.
IPDPS 2004 |
| 53 | | Alexander Thomas,
Thomas Zander,
Jürgen Becker:
Adaptive DMA-based I/O interfaces for data stream handling in multi-grained reconfigurable hardware architectures.
SBCCI 2004: 141-146 |
| 52 | | Michael Hübner,
Tobias Becker,
Jürgen Becker:
Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration.
SBCCI 2004: 28-32 |
| 51 | | Jürgen Becker:
Dagstuhl-Seminar "Dynamically and Partially Reconfigurable Architectures".
it - Information Technology 46(4): 218-225 (2004) |
| 2003 |
|---|
| 50 | | Jürgen Becker,
Alexander Thomas,
Martin Vorbach,
Volker Baumgarten:
An Industrial/Academic Configurable System-on-Chip Project (CSoC): Coarse-Grain XXP-/Leon-Based Architecture Integration.
DATE 2003: 11120-11121 |
| 49 | | Jürgen Becker,
Martin Vorbach:
PACT XPP Architecture in Adaptive System-on-Chip Integration.
Engineering of Reconfigurable Systems and Algorithms 2003: 21-30 |
| 48 | | Martin Vorbach,
Jürgen Becker:
Reconfigurable Processor Architectures for Mobile Phones.
IPDPS 2003: 181 |
| 47 | | Jürgen Becker,
Martin Vorbach:
Architecture, Memory and Interface Technology Integration of an Industrial/Academic Configurable System-on-Chip (CSoC).
ISVLSI 2003: 107-112 |
| 46 | | Jens E. Becker,
Carsten Bieser,
Alexander Thomas,
Klaus D. Müller-Glaser,
Jürgen Becker:
Hardware/Software Co-Training by FPGA/ASIC Synthesis and programming of a RISC Microprocessor-Core.
MSE 2003: 134-135 |
| 45 | | Jürgen Becker,
Alexander Thomas,
Maik Scheer:
Efficient Processor Instruction Set Extension by Asynchronous Reconfigurable Datapath Integration.
SBCCI 2003: 237-242 |
| 44 | | Jürgen Becker,
Michael Hübner,
Michael Ullmann:
Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-Offs and Limitations.
SBCCI 2003: 283-288 |
| 43 | | Jürgen Becker,
Michael Hübner,
Michael Ullmann:
Real-Time Dynamically Run-Time Reconfiguration for Power-/Cost-optimized Virtex FPGA Realizations.
VLSI-SOC 2003: 129- |
| 42 | | Jürgen Becker,
Alexander Thomas,
Maik Scheer:
Datapath and Compiler Integration of Coarse-grain Reconfigurable XPP-Arrays into Pipelined RISC Processors.
VLSI-SOC 2003: 288- |
| 41 | | Jürgen Becker,
Reiner W. Hartenstein:
Configware and morphware going mainstream.
Journal of Systems Architecture 49(4-6): 127-142 (2003) |
| 2002 |
|---|
| 40 | | Chun Hok Ho,
M. P. Leong,
Philip Heng Wai Leong,
Jürgen Becker,
Manfred Glesner:
Rapid Prototyping of FPGA Based Floating Point DSP Systems.
IEEE International Workshop on Rapid System Prototyping 2002: 19-24 |
| 2001 |
|---|
| 39 | | Jürgen Becker,
Nicolas Liebau,
Thilo Pionteck,
Manfred Glesner:
Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures.
FPL 2001: 584-589 |
| 38 | | Amar Mukherjee,
Nitin Motgi,
Jürgen Becker,
A. Friebe,
C. Habermann,
Manfred Glesner:
Prototyping of Efficient Hardware Algorithms for Data Compression in Future Communication Systems.
IEEE International Workshop on Rapid System Prototyping 2001: 58-63 |
| 37 | | Jochen Mades,
Thomas Schneider,
André Windisch,
Thomas Hollstein,
Jürgen Becker,
Manfred Glesner:
Concept of a Joint University/Industry Course for Mixed-Signal System-On-Chip Design.
MSE 2001: 2-3 |
| 36 | | Leandro Soares Indrusiak,
Jürgen Becker,
Manfred Glesner,
Ricardo Augusto da Luz Reis:
Distributed Collaborative Design over Cave2 Framework.
VLSI-SOC 2001: 97-108 |
| 35 | | Jürgen Becker,
Manfred Glesner:
A Parallel Dynamically Reconfigurable Architecture Designed for Flexible Application-Tailored Hardware/Software Systems in Future Mobile Communication.
The Journal of Supercomputing 19(1): 105-127 (2001) |
| 2000 |
|---|
| 34 | | Ahmad Alsolaim,
Janusz A. Starzyk,
Jürgen Becker,
Manfred Glesner:
Architecture and Application of a Dynamically Reconfigurable Hardware Array for Future Mobile Communication Systems.
FCCM 2000: 205-216 |
| 33 | | Jürgen Becker,
Thilo Pionteck,
Manfred Glesner:
DReAM: A Dynamically Reconfigurable Architecture for Future Mobile Communications Applications.
FPL 2000: 312-321 |
| 32 | | Frank-Michael Renner,
Jürgen Becker,
Manfred Glesner:
Field Programmable Communication Emulation and Optimization for Embedded System Design.
FPL 2000: 58-67 |
| 31 | | Frank-Michael Renner,
Jürgen Becker,
Manfred Glesner:
Automated Communication Synthesis for Architecture-Precise Rapid Prototyping of Real-Time Embedded Systems.
IEEE International Workshop on Rapid System Prototyping 2000: 154-159 |
| 30 | | Jürgen Becker,
Lukusa D. Kabulepa,
Frank-Michael Renner,
Manfred Glesner:
Simulation and Rapid Prototyping of Flexible Systems-on-a-Chip for Future Mobile Communication Applications.
IEEE International Workshop on Rapid System Prototyping 2000: 160- |
| 29 | | Jürgen Becker,
Manfred Glesner,
Ahmad Alsolaim,
Janusz A. Starzyk:
Fast Communication Mechanisms in Coarse-grained Dynamically Reconfigurable Array Architectures.
PDPTA 2000 |
| 28 | | Jürgen Becker,
Manfred Glesner:
IP-based Application Mapping Techniques for Dynamically Reconfigurable Hardware Architectures.
PDPTA 2000 |
| 27 | | Frank-Michael Renner,
Jürgen Becker,
Andreas Kirschbaum,
Manfred Glesner:
Synthese von Kommunikationsstrukturen und architekturgenaues Rapid-Prototyping eingebetteter Echtzeitsysteme (Communication Synthesis and Architecture-Precise Rapid Prototyping of Embedded systems with Hard Real-Time Constraints).
it+ti - Informationstechnik und Technische Informatik 42(2): 27-33 (2000) |
| 1999 |
|---|
| 26 | | Marc Theisen,
Jürgen Becker,
Manfred Glesner,
Tri Caohuu:
Parallel Hardware Compilation in Complex Hardware/Software Systems based on High-Level Code Transformations.
ARCS 1999: 143-154 |
| 25 | | Tri Caohuu,
Thuy Trong Le,
Manfred Glesner,
Jürgen Becker:
Dynamically Reconfigurable Reduced Crossbar: A Novel Approach to Large Scale Switching.
FPL 1999: 507-513 |
| 24 | | Frank-Michael Renner,
Jürgen Becker,
Manfred Glesner:
Communication Performance Models for Architecture-Precise Prototyping of Real-Time Embedded Systems.
IEEE International Workshop on Rapid System Prototyping 1999: 108-113 |
| 23 | | Andreas Kirschbaum,
Jürgen Becker,
Manfred Glesner:
ILP-Based Board-Level Routing of Multi-Terminal Nets for Prototyping Reconfigurable Interconnect.
VLSI 1999: 659-670 |
| 1998 |
|---|
| 22 | | Jürgen Becker,
Reiner W. Hartenstein,
Michael Herz,
Ulrich Nageldinger:
Parallelization in Co-Compilation for Configurable Accelerators.
ASP-DAC 1998: 23-33 |
| 21 | | Thomas Hollstein,
Jürgen Becker,
Andreas Kirschbaum,
Manfred Glesner:
HiPART: a new hierarchical semi-interactive HW-/SW partitioning approach with fast debugging for real-time embedded systems.
CODES 1998: 29-33 |
| 20 | | Frank-Michael Renner,
Jürgen Becker,
Manfred Glesner:
An FPFA Implementation of a Magnetic Bearing Controller for Mechatronic Applications.
FPL 1998: 179-188 |
| 19 | | Jürgen Becker,
Andreas Kirschbaum,
Frank-Michael Renner,
Manfred Glesner:
Perspectives of Reconfigurable Computing in Research, Industry and Education.
FPL 1998: 39-48 |
| 18 | | Andreas Kirschbaum,
Jürgen Becker,
Manfred Glesner:
A Reconfigurable Hardware-Monitor for Communication Analysis in Distributed Real-Time Systems.
IPPS/SPDP Workshops 1998: 61-66 |
| 17 | | Jürgen Becker,
Reiner W. Hartenstein:
Real-Time Prototyping in Microprocessor/Accelerator Symbiosis.
International Workshop on Rapid System Prototyping 1998: 32-38 |
| 16 | | Andreas Kirschbaum,
Jürgen Becker,
Manfred Glesner:
Run-Time Monitoring of Communication Activities in a Rapid Prototyping Environment.
International Workshop on Rapid System Prototyping 1998: 52-57 |
| 1997 |
|---|
| 15 | | Reiner W. Hartenstein,
Jürgen Becker,
Michael Herz,
Ulrich Nageldinger:
A Novel Universal Sequencer Hardware.
ARCS 1997: 143-152 |
| 14 | | Reiner W. Hartenstein,
Jürgen Becker,
Michael Herz,
Ulrich Nageldinger:
A Novel Sequencer Hardware for Application Specific Computing.
ASAP 1997: 392-401 |
| 13 | | Reiner W. Hartenstein,
Jürgen Becker:
Performance Analysis in CoDe-X Partitioning for Structural Programmable Accelerators.
CODES 1997: 141-146 |
| 12 | | Reiner W. Hartenstein,
Jürgen Becker,
Michael Herz,
Ulrich Nageldinger:
Data scheduling to increase performance of parallel accelerators.
FPL 1997: 294-303 |
| 11 | | Reiner W. Hartenstein,
Jürgen Becker:
A Two-level Co-Design Framework for Xputer-based data-driven reconfigurable Accelerators.
HICSS (5) 1997: 125-134 |
| 10 | | Reiner W. Hartenstein,
Jürgen Becker:
Hardware/Software Co-Design for Data-Driven Xputer-based Accelerators.
VLSI Design 1997: 146-150 |
| 1996 |
|---|
| 9 | | Reiner W. Hartenstein,
Jürgen Becker,
Michael Herz,
Rainer Kress,
Ulrich Nageldinger:
A Synthesis System For Bus-Based Wavefront Array Architectures.
ASAP 1996: 274-283 |
| 8 | | Reiner W. Hartenstein,
Jürgen Becker,
Rainer Kress:
Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine.
CODES 1996: 77-84 |
| 7 | | Reiner W. Hartenstein,
Jürgen Becker,
Rainer Kress:
Two-Level Hardware/Software Partitioning Using CoDe-X.
ECBS 1996: 395- |
| 6 | | Reiner W. Hartenstein,
Jürgen Becker,
Rainer Kress:
Custom Computing Machines vs. Hardware/Software Codesign: From a globalized point of view.
FPL 1996: 65-76 |
| 5 | | Reiner W. Hartenstein,
Jürgen Becker,
Michael Herz,
Rainer Kress,
Ulrich Nageldinger:
A Partitioning Programming Environment for a Novel Parallel Architecture.
IPPS 1996: 544-548 |
| 4 | | Reiner W. Hartenstein,
Jürgen Becker,
Rainer Kress,
Helmut Reinig:
CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework.
VLSI Design 1996: 81-84 |
| 3 | | Reiner W. Hartenstein,
Jürgen Becker,
Rainer Kress,
Helmut Reinig:
High-performance computing using a reconfigurable accelerator.
Concurrency - Practice and Experience 8(6): 429-443 (1996) |
| 1995 |
|---|
| 2 | | Reiner W. Hartenstein,
Jürgen Becker,
Rainer Kress,
Helmut Reinig,
Karin Schmidt:
A Parallelizing Compilation Method for the Map-oriented Machine.
ASAP 1995: 129-132 |
| 1994 |
|---|
| 1 | | Andreas Ast,
Jürgen Becker,
Reiner W. Hartenstein,
Rainer Kress,
Helmut Reinig,
Karin Schmidt:
Data-Procedural Languages for FPL-based Machines.
FPL 1994: 183-195 |
