2009 | ||
---|---|---|
41 | Shuichi Sakai, Hidetoshi Onodera, Hiroto Yasuura, James C. Hoe: Dependable VLSI: device, design and architecture: how should they cooperate? ASP-DAC 2009: 859-860 | |
40 | Peter A. Milder, James C. Hoe, Markus Püschel: Automatic generation of streaming datapaths for arbitrary fixed permutations. DATE 2009: 1118-1123 | |
39 | Brian T. Gold, Babak Falsafi, James C. Hoe: Chip-Level Redundancy in Distributed Shared-Memory Multiprocessors. PRDC 2009: 195-201 | |
38 | Markus Püschel, Peter A. Milder, James C. Hoe: Permuting streaming data using RAMs. J. ACM 56(2): (2009) | |
37 | Eric S. Chung, Michael Papamichael, Eriko Nurvitadhi, James C. Hoe, Ken Mai, Babak Falsafi: ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs. TRETS 2(2): (2009) | |
2008 | ||
36 | Peter A. Milder, Franz Franchetti, James C. Hoe, Markus Püschel: Formal datapath representation and manipulation for implementing DSP transforms. DAC 2008: 385-390 | |
35 | Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai: A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs. FPGA 2008: 77-86 | |
34 | Franz Franchetti, Yevgen Voronenko, Peter A. Milder, Srinivas Chellappa, Marek R. Telgarsky, Hao Shen, Paolo D'Alberto, Frédéric de Mesmay, James C. Hoe, José M. F. Moura, Markus Püschel: Domain-specific library generation for parallel software and hardware platforms. IPDPS 2008: 1-5 | |
33 | Patrick Schaumont, Krste Asanovic, James C. Hoe: MEMOCODE 2008 Co-Design Contest. MEMOCODE 2008: 151-154 | |
2007 | ||
32 | Paolo D'Alberto, Peter A. Milder, Aliaksei Sandryhaila, Franz Franchetti, James C. Hoe, José M. F. Moura, Markus Püschel, Jeremy R. Johnson: Generating FPGA-Accelerated DFT Libraries. FCCM 2007: 173-184 | |
31 | Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai: PROToFLEX: FPGA-accelerated Hybrid Functional Simulator. IPDPS 2007: 1-6 | |
30 | Forrest Brewer, James C. Hoe: MEMOCODE 2007 Co-Design Contest. MEMOCODE 2007: 91-94 | |
29 | Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Falsafi, James C. Hoe: Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding. MICRO 2007: 197-209 | |
28 | Jangwoo Kim, Jared C. Smolens, Babak Falsafi, James C. Hoe: PAI: A Lightweight Mechanism for Single-Node Memory Recovery in DSM Servers. PRDC 2007: 298-305 | |
27 | John Wawrzynek, David A. Patterson, Mark Oskin, Shih-Lien Lu, Christoforos E. Kozyrakis, James C. Hoe, Derek Chiou, Krste Asanovic: RAMP: Research Accelerator for Multiple Processors. IEEE Micro 27(2): 46-57 (2007) | |
26 | Peter Tummeltshammer, James C. Hoe, Markus Püschel: Time-Multiplexed Multiple-Constant Multiplication. IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1551-1563 (2007) | |
2006 | ||
25 | Peter A. Milder, Mohammad Ahmad, James C. Hoe, Markus Püschel: Fast and accurate resource estimation of automatically generated custom DFT IP cores. FPGA 2006: 211-220 | |
24 | Thomas F. Wenisch, Roland E. Wunderlich, Babak Falsafi, James C. Hoe: Statistical sampling of microarchitecture simulation. IPDPS 2006 | |
23 | Thomas F. Wenisch, Roland E. Wunderlich, Babak Falsafi, James C. Hoe: Simulation sampling with live-points. ISPASS 2006: 2-12 | |
22 | Jared C. Smolens, Brian T. Gold, Babak Falsafi, James C. Hoe: Reunion: Complexity-Effective Multicore Redundancy. MICRO 2006: 223-234 | |
21 | Roland E. Wunderlich, Thomas F. Wenisch, Babak Falsafi, James C. Hoe: Statistical sampling of microarchitecture simulation. ACM Trans. Model. Comput. Simul. 16(3): 197-224 (2006) | |
20 | Thomas F. Wenisch, Roland E. Wunderlich, Michael Ferdman, Anastassia Ailamaki, Babak Falsafi, James C. Hoe: SimFlex: Statistical Sampling of Computer System Simulation. IEEE Micro 26(4): 18-31 (2006) | |
2005 | ||
19 | Grace Nordin, Peter A. Milder, James C. Hoe, Markus Püschel: Automatic generation of customized discrete fourier transform IPs. DAC 2005: 471-474 | |
18 | Thomas F. Wenisch, Roland E. Wunderlich, Babak Falsafi, James C. Hoe: TurboSMARTS: accurate microarchitecture simulation sampling in minutes. SIGMETRICS 2005: 408-409 | |
17 | Brian T. Gold, Jangwoo Kim, Jared C. Smolens, Eric S. Chung, Vasileios Liaskovitis, Eriko Nurvitadhi, Babak Falsafi, James C. Hoe, Andreas Nowatzyk: TRUSS: A Reliable, Scalable Server Architecture. IEEE Micro 25(6): 51-59 (2005) | |
2004 | ||
16 | Jared C. Smolens, Brian T. Gold, Jangwoo Kim, Babak Falsafi, James C. Hoe, Andreas Nowatzyk: Fingerprinting: bounding soft-error detection latency and bandwidth. ASPLOS 2004: 224-234 | |
15 | Peter Tummeltshammer, James C. Hoe, Markus Püschel: Multiple constant multiplication by time-multiplexed mapping of addition chains. DAC 2004: 826-829 | |
14 | Roland E. Wunderlich, James C. Hoe: In-system FPGA prototyping of an itanium microarchitecture. FPGA 2004: 255 | |
13 | Markus Püschel, Adam C. Zelinski, James C. Hoe: Custom-optimized multiplierless implementations of DSP algorithms. ICCAD 2004: 175-182 | |
12 | Roland E. Wunderlich, James C. Hoe: In-System FPGA Prototyping of an Itanium Microarchitecture. ICCD 2004: 288-294 | |
11 | Grace Nordin, James C. Hoe: Synchronous extensions to operation centric hardware description languages. MEMOCODE 2004: 49-56 | |
10 | Jared C. Smolens, Jangwoo Kim, James C. Hoe, Babak Falsafi: Efficient Resource Sharing in Concurrent Error Detecting Superscalar Microarchitectures. MICRO 2004: 257-268 | |
9 | Jared C. Smolens, Brian T. Gold, Jangwoo Kim, Babak Falsafi, James C. Hoe, Andreas Nowatzyk: Fingerprinting: Bounding Soft-Error-Detection Latency and Bandwidth. IEEE Micro 24(6): 22-29 (2004) | |
8 | James C. Hoe, Arvind: Operation-centric hardware description and synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 23(9): 1277-1288 (2004) | |
7 | Nikolaos Hardavellas, Stephen Somogyi, Thomas F. Wenisch, Roland E. Wunderlich, Shelley Chen, Jangwoo Kim, Babak Falsafi, James C. Hoe, Andreas Nowatzyk: SimFlex: a fast, accurate, flexible full-system simulation framework for performance evaluation of server architecture. SIGMETRICS Performance Evaluation Review 31(4): 31-34 (2004) | |
2003 | ||
6 | Joydeep Ray, James C. Hoe: High-level modeling and FPGA prototyping of microprocessors. FPGA 2003: 100-107 | |
5 | Roland E. Wunderlich, Thomas F. Wenisch, Babak Falsafi, James C. Hoe: SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling. ISCA 2003: 84-95 | |
2001 | ||
4 | Joydeep Ray, James C. Hoe, Babak Falsafi: Dual use of superscalar datapath for transient-fault detection and recovery. MICRO 2001: 214-224 | |
2000 | ||
3 | James C. Hoe, Arvind: Synthesis of Operation-Centric Hardware Descriptions. ICCAD 2000: 511-518 | |
1999 | ||
2 | James C. Hoe, Arvind: Hardware Synthesis from Term Rewriting Systems. VLSI 1999: 595-619 | |
1995 | ||
1 | Derek Chiou, Boon Seong Ang, Robert Greiner, Arvind, James C. Hoe, Michael J. Beckerle, James E. Hicks, G. Andrew Boughton: START-NG: Delivering Seamless Parallel Computing. Euro-Par 1995: 101-116 |