Shih-Lien Lu

	2009
31		Keith A. Bowman, James Tschanz, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek De, Shekhar Y. Borkar: Circuit techniques for dynamic variation tolerance. DAC 2009: 4-7
30		Seung Eun Lee, Chris Wilkerson, Ming Zhang, Rajendra Yavatkar, Shih-Lien Lu, Nader Bagherzadeh: Low power adaptive pipeline based on instruction isolation. ISQED 2009: 788-793
29		Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Wei Wu, Shih-Lien Lu: Improving cache lifetime reliability at ultra-low voltages. MICRO 2009: 89-99
28		Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad Khellah, Shih-Lien Lu: Trading Off Cache Capacity for Low-Voltage Operation. IEEE Micro 29(1): 96-103 (2009)
	2008
27		Changjian Gao, Shih-Lien Lu: Novel FPGA based Haar classifier face detection algorithm acceleration. FPL 2008: 373-378
26		Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad Khellah, Shih-Lien Lu: Trading off Cache Capacity for Reliability to Enable Low Voltage Operation. ISCA 2008: 203-214
25		Shih-Lien Lu, Ravichandran Ramachandran: Carry Logic. Wiley Encyclopedia of Computer Science and Engineering 2008
24		Eriko Nurvitadhi, Jumnit Hong, Shih-Lien Lu: Active Cache Emulator. IEEE Trans. VLSI Syst. 16(3): 229-240 (2008)
23		Shih-Lien Lu, Peter Yiannacouras, Taeweon Suh, Rolf Kassa, Michael Konow: A Desktop Computer with a Reconfigurable Pentium®. TRETS 1(1): (2008)
	2007
22		Shih-Lien Lu, Peter Yiannacouras, Rolf Kassa, Michael Konow, Taeweon Suh: An FPGA-based Pentium in a complete desktop system. FPGA 2007: 53-59
21		Taeweon Suh, Shih-Lien Lu, Hsien-Hsin S. Lee: An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems. FPL 2007: 47-53
20		Wei Wu, Sheldon X.-D. Tan, Jun Yang, Shih-Lien Lu: Improving the reliability of on-chip data caches under process variations. ICCD 2007: 325-332
19		Patrick Ndai, Shih-Lien Lu, Dinesh Somasekhar, Kaushik Roy: Fine-Grained Redundancy in Adders. ISQED 2007: 317-321
18		John Wawrzynek, David A. Patterson, Mark Oskin, Shih-Lien Lu, Christoforos E. Kozyrakis, James C. Hoe, Derek Chiou, Krste Asanovic: RAMP: Research Accelerator for Multiple Processors. IEEE Micro 27(2): 46-57 (2007)
	2006
17		Jumnit Hong, Eriko Nurvitadhi, Shih-Lien Lu: Design, implementation, and verification of active cache emulator (ACE). FPGA 2006: 63-72
	2005
16		Chunrong Lai, Shih-Lien Lu, Yurong Chen, Trista Chen: Improving branch prediction accuracy with parallel conservative correctors. Conf. Computing Frontiers 2005: 334-341
15		Eriko Nurvitadhi, Nirut Chalainanont, Shih-Lien Lu: Characterization of L3 cache behavior of SPECjAppServer2002 and TPC-C. ICS 2005: 12-20
	2004
14		Chunrong Lai, Shih-Lien Lu: Efficient Victim Mechanism on Sector Cache Organization. Asia-Pacific Computer Systems Architecture Conference 2004: 16-29
13		Shih-Lien Lu: Speeding Up Processing with Approximation Circuits. IEEE Computer 37(3): 67-73 (2004)
	2003
12		Shih-Lien Lu, Konrad Lai: Implementation of HW$im - A Real-Time Configurable Cache Simulator. FPL 2003: 638-647
11		Shih-Chang Lai, Shih-Lien Lu: Hardware-based Pointer Data Prefetcher. ICCD 2003: 290-298
	2002
10		Shih-Chang Lai, Shih-Lien Lu, Jih-Kwon Peir: Ditto Processor. DSN 2002: 525-536
9		Jih-Kwon Peir, Shih-Chang Lai, Shih-Lien Lu, Jared Stark, Konrad Lai: Bloom filtering cache misses for accurate data speculation and prefetching. ICS 2002: 189-198
8		Steven Hsu, Shih-Lien Lu, Shih-Chang Lai, Ram Krishnamurthy, Konrad Lai: Dynamic addressing memory arrays with physical locality. MICRO 2002: 161-170
	2000
7		Tong Liu, Shih-Lien Lu: Performance improvement with circuit-level speculation. MICRO 2000: 348-355
	1998
6		Michael F. Miller, Kenneth J. Janik, Shih-Lien Lu: Non-Stalling CounterFlow Architecture. HPCA 1998: 334-341
	1997
5		Kenneth J. Janik, Shih-Lien Lu, Michael F. Miller: Advances of the Counterflow Pipeline Microarchitecture. HPCA 1997: 230-236
	1996
4		Ravichandran Ramachandran, Shih-Lien Lu: Efficient arithmetic using self-timing. IEEE Trans. VLSI Syst. 4(4): 445-454 (1996)
	1995
3		Shih-Lien Lu: Implementation of micropipelines in enable/disable CMOS differential logic. IEEE Trans. VLSI Syst. 3(2): 338-341 (1995)
2		Chih-Ming Chang, Shih-Lien Lu: Design of a static MIMD data flow processor using micropipelines. IEEE Trans. VLSI Syst. 3(3): 370-378 (1995)
	1988
1		Chung-Ping Wan, Bing J. Sheu, Shih-Lien Lu: Device and circuit simulation interface for an integrated VLSI design environment. IEEE Trans. on CAD of Integrated Circuits and Systems 7(9): 998-1004 (1988)

Coauthor Index

1	Alaa R. Alameldeen	[26] [28] [29]
2	Krste Asanovic	[18]
3	Nader Bagherzadeh	[30]
4	Shekhar Y. Borkar (Shekhar Borkar)	[31]
5	Keith A. Bowman	[31]
6	Nirut Chalainanont	[15]
7	Chih-Ming Chang	[2]
8	Trista Chen	[16]
9	Yurong Chen	[16]
10	Derek Chiou	[18]
11	Zeshan Chishti	[26] [28] [29]
12	Vivek De	[31]
13	Changjian Gao	[27]
14	Hongliang Gao	[26] [28]
15	James C. Hoe	[18]
16	Jumnit Hong	[17] [24]
17	Steven Hsu	[8]
18	Kenneth J. Janik	[5] [6]
19	Tanay Karnik	[31]
20	Rolf Kassa	[22] [23]
21	Muhammad Khellah	[26] [28]
22	Michael Konow	[22] [23]
23	Christoforos E. Kozyrakis (Christos Kozyrakis)	[18]
24	Ram Krishnamurthy	[8]
25	Chunrong Lai	[14] [16]
26	Konrad Lai (Konrad K. Lai)	[8] [9] [12]
27	Shih-Chang Lai	[8] [9] [10] [11]
28	Hsien-Hsin S. Lee	[21]
29	Seung Eun Lee	[30]
30	Tong Liu	[7]
31	Michael F. Miller	[5] [6]
32	Patrick Ndai	[19]
33	Eriko Nurvitadhi	[15] [17] [24]
34	Mark Oskin	[18]
35	David A. Patterson	[18]
36	Jih-Kwon Peir	[9] [10]
37	Ravichandran Ramachandran	[4] [25]
38	Kaushik Roy	[19]
39	Bing J. Sheu	[1]
40	Dinesh Somasekhar	[19]
41	Jared Stark	[9]
42	Taeweon Suh	[21] [22] [23]
43	Sheldon X.-D. Tan (Xiang-Dong Tan)	[20]
44	James Tschanz (James W. Tschanz)	[31]
45	Chung-Ping Wan	[1]
46	John Wawrzynek	[18]
47	Chris Wilkerson	[26] [28] [29] [30] [31]
48	Wei Wu	[20] [29]
49	Jun Yang	[20]
50	Rajendra Yavatkar	[30]
51	Peter Yiannacouras	[22] [23]
52	Ming Zhang	[30]

Colors in the list of coauthors