Vijaykrishnan Narayanan
List of publications from the DBLP Bibliography Server - FAQ
![]() | 2010 | |
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229 | ![]() ![]() ![]() ![]() ![]() ![]() | Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Total Power Optimization for Combinational Logic Using Genetic Algorithms. Signal Processing Systems 58(2): 145-160 (2010) |
2009 | ||
228 | ![]() ![]() ![]() ![]() ![]() ![]() | Michael DeBole, Krishnan Ramakrishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang, Yuan Xie, Yu Cao, Narayanan Vijaykrishnan: A framework for estimating NBTI degradation of microarchitectural components. ASP-DAC 2009: 455-460 |
227 | ![]() ![]() ![]() ![]() ![]() ![]() | Srinath Sridharan, Michael DeBole, Guangyu Sun, Yuan Xie, Vijaykrishnan Narayanan: A criticality-driven microarchitectural three dimensional (3D) floorplanner. ASP-DAC 2009: 763-768 |
226 | ![]() ![]() ![]() ![]() ![]() ![]() | Sungmin Bae, Prasanth Mangalagiri, Narayanan Vijaykrishnan: Exploiting clock skew scheduling for FPGA. DATE 2009: 1524-1529 |
225 | ![]() ![]() ![]() ![]() ![]() ![]() | Reetuparna Das, Soumya Eachempati, Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das: Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs. HPCA 2009: 175-186 |
224 | ![]() ![]() ![]() ![]() ![]() ![]() | Aditya Yanamandra, Mary Jane Irwin, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Sri Hari Krishna Narayanan: In-Network Caching for Chip Multiprocessors. HiPEAC 2009: 373-388 |
223 | ![]() ![]() ![]() ![]() ![]() ![]() | Suman Datta, Vijaykrishnan Narayanan: Green transistors to green architectures. ISLPED 2009: 429-430 |
222 | ![]() ![]() ![]() ![]() ![]() ![]() | Asit K. Mishra, Reetuparna Das, Soumya Eachempati, Ravishankar Iyer, Narayanan Vijaykrishnan, Chita R. Das: A case for dynamic frequency tuning in on-chip networks. MICRO 2009: 292-303 |
221 | ![]() ![]() ![]() ![]() ![]() ![]() | Jörg Henkel, Vijaykrishnan Narayanan, Sri Parameswaran, Roshan G. Ragel: Security and Dependability of Embedded Systems: A Computer Architects' Perspective. VLSI Design 2009: 30-32 |
220 | ![]() ![]() ![]() ![]() ![]() ![]() | Jie S. Hu, Feihui Li, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Compiler-assisted soft error detection under performance and energy constraints in embedded systems. ACM Trans. Embedded Comput. Syst. 8(4): (2009) |
219 | ![]() ![]() ![]() ![]() ![]() ![]() | Jungsub Kim, Lanping Deng, Prasanth Mangalagiri, Kevin M. Irick, Kanwaldeep Sobti, Mahmut T. Kandemir, Vijaykrishnan Narayanan, Chaitali Chakrabarti, Nikos Pitsianis, Xiaobai Sun: An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization. IEEE Trans. Computers 58(12): 1654-1667 (2009) |
218 | ![]() ![]() ![]() ![]() ![]() ![]() | Madhu Mutyam, Feng Wang, Krishnan Ramakrishnan, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Yuan Xie, Mary Jane Irwin: Process-Variation-Aware Adaptive Cache Architecture and Management. IEEE Trans. Computers 58(7): 865-877 (2009) |
217 | ![]() ![]() ![]() ![]() ![]() ![]() | Rajaraman Ramanarayanan, Vijay Degalahal, Krishnan Ramakrishnan, Jung Sub Kim, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Kenan Unlu: Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits. IEEE Trans. Dependable Sec. Comput. 6(3): 202-216 (2009) |
216 | ![]() ![]() ![]() ![]() ![]() ![]() | Michael DeBole, Krishnan Ramakrishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang, Yuan Xie, Yu Cao, Narayanan Vijaykrishnan: New-Age: A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural Components. International Journal of Parallel Programming 37(4): 417-431 (2009) |
2008 | ||
215 | ![]() ![]() ![]() ![]() ![]() ![]() | Vijaykrishnan Narayanan, C. P. Ravikumar, Jörg Henkel, Ali Keshavarzi, Vojin G. Oklobdzija, Barry M. Pangrle: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008 ACM 2008 |
214 | ![]() ![]() ![]() ![]() ![]() ![]() | Prasanth Mangalagiri, Karthik Sarpatwari, Aditya Yanamandra, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Osama Awadel Karim: A low-power phase change memory based hybrid cache architecture. ACM Great Lakes Symposium on VLSI 2008: 395-398 |
213 | ![]() ![]() ![]() ![]() ![]() ![]() | Niranjan Soundararajan, Aditya Yanamandra, Chrysostomos Nicopoulos, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin: Analysis and solutions to issue queue process variation. DSN 2008: 11-21 |
212 | ![]() ![]() ![]() ![]() ![]() ![]() | Kevin M. Irick, Michael DeBole, Vijaykrishnan Narayanan, Aman Gayasen: A Hardware Efficient Support Vector Machine Architecture for FPGA. FCCM 2008: 304-305 |
211 | ![]() ![]() ![]() ![]() ![]() ![]() | Prasanth Mangalagiri, Sungmin Bae, Krishnan Ramakrishnan, Yuan Xie, Vijaykrishnan Narayanan: Thermal-aware reliability analysis for platform FPGAs. ICCAD 2008: 722-727 |
210 | ![]() ![]() ![]() ![]() ![]() ![]() | Krishnan Ramakrishnan, Xiaoxia Wu, Narayanan Vijaykrishnan, Yuan Xie: Comparative analysis of NBTI effects on low power and high performance flip-flops. ICCD 2008: 200-205 |
209 | ![]() ![]() ![]() ![]() ![]() ![]() | Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das: MIRA: A Multi-layered On-Chip Interconnect Router Architecture. ISCA 2008: 251-261 |
208 | ![]() ![]() ![]() ![]() ![]() ![]() | Niranjan Soundararajan, Narayanan Vijaykrishnan, Anand Sivasubramaniam: Impact of dynamic voltage and frequency scaling on the architectural vulnerability of GALS architectures. ISLPED 2008: 351-356 |
207 | ![]() ![]() ![]() ![]() ![]() ![]() | Krishnan Ramakrishnan, R. Rajaraman, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin, Kenan Unlu: Hierarchical Soft Error Estimation Tool (HSEET). ISQED 2008: 680-683 |
206 | ![]() ![]() ![]() ![]() ![]() ![]() | Suresh Srinivasan, Krishnan Ramakrishnan, Prasanth Mangalagiri, Yuan Xie, Vijaykrishnan Narayanan, Mary Jane Irwin, Karthik Sarpatwari: Toward Increasing FPGA Lifetime. IEEE Trans. Dependable Sec. Comput. 5(2): 115-127 (2008) |
205 | ![]() ![]() ![]() ![]() ![]() ![]() | Yuh-Fang Tsai, Feng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: Design Space Exploration for 3-D Cache. IEEE Trans. VLSI Syst. 16(4): 444-455 (2008) |
204 | ![]() ![]() ![]() ![]() ![]() ![]() | Shengqi Yang, Wenping Wang, Tiehan Lv, Wayne Wolf, Narayanan Vijaykrishnan, Yuan Xie: Case Study of Reliability-Aware and Low-Power Design. IEEE Trans. VLSI Syst. 16(7): 861-873 (2008) |
203 | ![]() ![]() ![]() ![]() ![]() ![]() | Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Arifur Rahman: Designing a 3-D FPGA: Switch Box Architecture and Thermal Issues. IEEE Trans. VLSI Syst. 16(7): 882-893 (2008) |
202 | ![]() ![]() ![]() ![]() ![]() ![]() | Vijaykrishnan Narayanan: Editorial. JETC 4(2): (2008) |
2007 | ||
201 | ![]() ![]() ![]() ![]() ![]() ![]() | Diana Marculescu, Anand Raghunathan, Ali Keshavarzi, Vijaykrishnan Narayanan: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007 ACM 2007 |
200 | ![]() ![]() ![]() ![]() ![]() ![]() | Madhu Mutyam, Narayanan Vijaykrishnan: Working with process variation aware caches. DATE 2007: 1152-1157 |
199 | ![]() ![]() ![]() ![]() ![]() ![]() | Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Tamer Ragheb, Greg M. Link, Narayanan Vijaykrishnan, Yehia Massoud: Thermally robust clocking schemes for 3D integrated circuits. DATE 2007: 1206-1211 |
198 | ![]() ![]() ![]() ![]() ![]() ![]() | Soumya Eachempati, Arthur Nieuwoudt, Aman Gayasen, Narayanan Vijaykrishnan, Yehia Massoud: Assessing carbon nanotube bundle interconnect for future FPGA architectures. DATE 2007: 307-312 |
197 | ![]() ![]() ![]() ![]() ![]() ![]() | Kevin M. Irick, Michael DeBole, Vijaykrishnan Narayanan, Rajeev Sharma, Hankyu Moon, Satish Mummareddy: A Unified Streaming Architecture for Real Time Face Detection and Gender Classification. FPL 2007: 267-272 |
196 | ![]() ![]() ![]() ![]() ![]() ![]() | Feng Wang, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan: Variation-aware task allocation and scheduling for MPSoC. ICCAD 2007: 598-603 |
195 | ![]() ![]() ![]() ![]() ![]() ![]() | Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, Narayanan Vijaykrishnan: FPGA routing architecture analysis under variations. ICCD 2007: 152-157 |
194 | ![]() ![]() ![]() ![]() ![]() ![]() | Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Reetuparna Das, Yuan Xie, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das: A novel dimensionally-decomposed router for on-chip communication in 3D architectures. ISCA 2007: 138-149 |
193 | ![]() ![]() ![]() ![]() ![]() ![]() | Amol Mupid, Madhu Mutyam, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Variation Analysis of CAM Cells. ISQED 2007: 333-338 |
192 | ![]() ![]() ![]() ![]() ![]() ![]() | Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Tamer Ragheb, Greg M. Link, Narayanan Vijaykrishnan, Yehia Massoud: Mitigating Thermal Effects on Clock Skew with Dynamically Adaptive Drivers. ISQED 2007: 67-72 |
191 | ![]() ![]() ![]() ![]() ![]() ![]() | Krishnan Ramakrishnan, R. Rajaraman, S. Suresh, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Variation Impact on SER of Combinational Circuits. ISQED 2007: 911-916 |
190 | ![]() ![]() ![]() ![]() ![]() ![]() | Andrew J. Ricketts, Madhu Mutyam, Narayanan Vijaykrishnan, Mary Jane Irwin: Investigating Simple Low Latency Reliable Multiported Register Files. ISVLSI 2007: 375-382 |
189 | ![]() ![]() ![]() ![]() ![]() ![]() | Soumya Eachempati, Narayanan Vijaykrishnan, Arthur Nieuwoudt, Yehia Massoud: Impact of Process Variations on Carbon Nanotube Bundle Interconnect for Future FPGA Architectures. ISVLSI 2007: 516-517 |
188 | ![]() ![]() ![]() ![]() ![]() ![]() | Balaji Vaidyanathan, Wei-Lun Hung, Feng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: Architecting Microprocessor Components in 3D Design Space. VLSI Design 2007: 103-108 |
187 | ![]() ![]() ![]() ![]() ![]() ![]() | Krishnan Ramakrishnan, S. Suresh, Narayanan Vijaykrishnan, Mary Jane Irwin: Impact of NBTI on FPGAs. VLSI Design 2007: 717-722 |
186 | ![]() ![]() ![]() ![]() ![]() ![]() | Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Thermal-Aware Task Allocation and Scheduling for Embedded Systems CoRR abs/0710.4660: (2007) |
185 | ![]() ![]() ![]() ![]() ![]() ![]() | Yuh-Fang Tsai, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin: Leakage-Aware Interconnect for On-Chip Network CoRR abs/0710.4731: (2007) |
184 | ![]() ![]() ![]() ![]() ![]() ![]() | Greg M. Link, Narayanan Vijaykrishnan: Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip CoRR abs/0710.4764: (2007) |
183 | ![]() ![]() ![]() ![]() ![]() ![]() | Tao Li, Lizy Kurian John, Anand Sivasubramaniam, Narayanan Vijaykrishnan, Juan Rubio: OS-Aware Branch Prediction: Improving Microprocessor Control Flow Prediction for Operating Systems. IEEE Trans. Computers 56(1): 2-17 (2007) |
182 | ![]() ![]() ![]() ![]() ![]() ![]() | Richard R. Brooks, P. Y. Govindaraju, Matthew Pirretti, Narayanan Vijaykrishnan, Mahmut T. Kandemir: On the Detection of Clones in Sensor Networks Using Random Key Predistribution. IEEE Transactions on Systems, Man, and Cybernetics, Part C 37(6): 1246-1258 (2007) |
181 | ![]() ![]() ![]() ![]() ![]() ![]() | Aman Gayasen, Suresh Srinivasan, Narayanan Vijaykrishnan, Mahmut T. Kandemir: Design of power-aware FPGA fabrics. IJES 3(1/2): 52-64 (2007) |
180 | ![]() ![]() ![]() ![]() ![]() ![]() | Soontae Kim, Narayanan Vijaykrishnan, Mary Jane Irwin: Reducing non-deterministic loads in low-power caches via early cache set resolution. Microprocessors and Microsystems 31(5): 293-301 (2007) |
179 | ![]() ![]() ![]() ![]() ![]() ![]() | Yuan Xie, Lin Li, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Reliability-aware Co-synthesis for Embedded Systems. VLSI Signal Processing 49(1): 87-99 (2007) |
2006 | ||
178 | ![]() ![]() ![]() ![]() ![]() ![]() | Gang Qu, Yehea I. Ismail, Narayanan Vijaykrishnan, Hai Zhou: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006 ACM 2006 |
177 | ![]() ![]() ![]() ![]() ![]() ![]() | Balaji Vaidyanathan, Suresh Srinivasan, Yuan Xie, Narayanan Vijaykrishnan, Rong Luo: Leakage Optimized DECAP Design for FPGAs. APCCAS 2006: 960-963 |
176 | ![]() ![]() ![]() ![]() ![]() ![]() | Guilin Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Object duplication for improving reliability. ASP-DAC 2006: 140-145 |
175 | ![]() ![]() ![]() ![]() ![]() ![]() | Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, Narayanan Vijaykrishnan, Karthik Sarpatwari: FLAW: FPGA lifetime awareness. DAC 2006: 630-635 |
174 | ![]() ![]() ![]() ![]() ![]() ![]() | Andrew J. Ricketts, Kevin M. Irick, Narayanan Vijaykrishnan, Mary Jane Irwin: Priority scheduling in digital microfluidics-based biochips. DATE 2006: 329-334 |
173 | ![]() ![]() ![]() ![]() ![]() ![]() | Feng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: On-chip bus thermal analysis and optimization. DATE 2006: 850-855 |
172 | ![]() ![]() ![]() ![]() ![]() ![]() | Dongkook Park, Chrysostomos Nicopoulos, Jongman Kim, Narayanan Vijaykrishnan, Chita R. Das: Exploring Fault-Tolerant Network-on-Chip Architectures. DSN 2006: 93-104 |
171 | ![]() ![]() ![]() ![]() ![]() ![]() | Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Arif Rahman: Switch Box Architectures for Three-Dimensional FPGAs. FCCM 2006: 335-336 |
170 | ![]() ![]() ![]() ![]() ![]() ![]() | Priya Sundararajan, Aman Gayasen, Narayanan Vijaykrishnan, Tim Tuan: Thermal characterization and optimization in platform FPGAs. ICCAD 2006: 443-447 |
169 | ![]() ![]() ![]() ![]() ![]() ![]() | Feihui Li, Chrysostomos Nicopoulos, Thomas D. Richardson, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir: Design and Management of 3D Chip Multiprocessors Using Network-in-Memory. ISCA 2006: 130-141 |
168 | ![]() ![]() ![]() ![]() ![]() ![]() | Greg M. Link, Narayanan Vijaykrishnan: Thermal Trends in Emerging Technologies. ISQED 2006: 625-632 |
167 | ![]() ![]() ![]() ![]() ![]() ![]() | Ing-Chao Lin, Suresh Srinivasan, Narayanan Vijaykrishnan, Nagu R. Dhanwada: Transaction Level Error Susceptibility Model for Bus Based SoC Architectures. ISQED 2006: 775-780 |
166 | ![]() ![]() ![]() ![]() ![]() ![]() | Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: Interconnect and Thermal-aware Floorplanning for 3D Microprocessors. ISQED 2006: 98-104 |
165 | ![]() ![]() ![]() ![]() ![]() ![]() | Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan, Yuan Xie: Reliability-Aware SOC Voltage Islands Partition and Floorplan. ISVLSI 2006: 343-348 |
164 | ![]() ![]() ![]() ![]() ![]() ![]() | Madhu Mutyam, Melvin Eze, Narayanan Vijaykrishnan, Yuan Xie: Delay and Energy Efficient Data Transmission for On-Chip Buses. ISVLSI 2006: 355-360 |
163 | ![]() ![]() ![]() ![]() ![]() ![]() | Suresh Srinivasan, Narayanan Vijaykrishnan: Variation Aware Placement for FPGAs. ISVLSI 2006: 422-423 |
162 | ![]() ![]() ![]() ![]() ![]() ![]() | Theo Theocharides, Narayanan Vijaykrishnan, Mary Jane Irwin: A Parallel Architecture for Hardware Face Detection. ISVLSI 2006: 452-453 |
161 | ![]() ![]() ![]() ![]() ![]() ![]() | Madhu Mutyam, Feihui Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Compiler-directed thermal management for VLIW functional units. LCTES 2006: 163-172 |
160 | ![]() ![]() ![]() ![]() ![]() ![]() | Chrysostomos Nicopoulos, Dongkook Park, Jongman Kim, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das: ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers. MICRO 2006: 333-346 |
159 | ![]() ![]() ![]() ![]() ![]() ![]() | R. Rajaraman, Jungsub Kim, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: SEAT-LA: A Soft Error Analysis Tool for Combinational Logic. VLSI Design 2006: 499-502 |
158 | ![]() ![]() ![]() ![]() ![]() ![]() | Thomas D. Richardson, Chrysostomos Nicopoulos, Dongkook Park, Narayanan Vijaykrishnan, Yuan Xie, Chita R. Das, Vijay Degalahal: A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks. VLSI Design 2006: 657-664 |
157 | ![]() ![]() ![]() ![]() ![]() ![]() | Wei Zhang, Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Reducing dynamic and leakage energy in VLIW architectures. ACM Trans. Embedded Comput. Syst. 5(1): 1-28 (2006) |
156 | ![]() ![]() ![]() ![]() ![]() ![]() | Narayanan Vijaykrishnan, Yuan Xie: Reliability Concerns in Embedded System Designs. IEEE Computer 39(1): 118-120 (2006) |
155 | ![]() ![]() ![]() ![]() ![]() ![]() | Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne Wolf: An efficient architecture for motion estimation and compensation in the transform domain. IEEE Trans. Circuits Syst. Video Techn. 16(2): 191-201 (2006) |
154 | ![]() ![]() ![]() ![]() ![]() ![]() | Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin: Inverse discrete cosine transform architecture exploiting sparseness and symmetry properties. IEEE Trans. Circuits Syst. Video Techn. 16(5): 655-662 (2006) |
153 | ![]() ![]() ![]() ![]() ![]() ![]() | Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, Rajarathnam Chandramouli: Block-based frequency scalable technique for efficient hierarchical coding. IEEE Transactions on Signal Processing 54(7): 2559-2566 (2006) |
152 | ![]() ![]() ![]() ![]() ![]() ![]() | Matthew Pirretti, Sencun Zhu, Narayanan Vijaykrishnan, Patrick McDaniel, Mahmut T. Kandemir, Richard R. Brooks: The Sleep Deprivation Attack in Sensor Networks: Analysis and Methods of Defense. IJDSN 2(3): 267-287 (2006) |
2005 | ||
151 | ![]() ![]() ![]() ![]() ![]() ![]() | Jongman Kim, Dongkook Park, Chrysostomos Nicopoulos, Narayanan Vijaykrishnan, Chita R. Das: Design and analysis of an NoC architecture from performance, reliability and energy perspective. ANCS 2005: 173-182 |
150 | ![]() ![]() ![]() ![]() ![]() ![]() | Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Designing reliable circuit in the presence of soft errors. ASP-DAC 2005: 1 |
149 | ![]() ![]() ![]() ![]() ![]() ![]() | E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan: Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs. ASP-DAC 2005: 1200-1203 |
148 | ![]() ![]() ![]() ![]() ![]() ![]() | Shengqi Yang, Wayne Wolf, Wenping Wang, Narayanan Vijaykrishnan, Yuan Xie: Low-leakage robust SRAM cell design for sub-100nm technologies. ASP-DAC 2005: 539-544 |
147 | ![]() ![]() ![]() ![]() ![]() ![]() | Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykrishnan, Tim Tuan: Leakage control in FPGA routing fabric. ASP-DAC 2005: 661-664 |
146 | ![]() ![]() ![]() ![]() ![]() ![]() | Jongman Kim, Dongkook Park, Theo Theocharides, Narayanan Vijaykrishnan, Chita R. Das: A low latency router supporting adaptivity for on-chip interconnects. DAC 2005: 559-564 |
145 | ![]() ![]() ![]() ![]() ![]() ![]() | Aman Gayasen, Narayanan Vijaykrishnan, Mary Jane Irwin: Exploring technology alternatives for nano-scale FPGA interconnects. DAC 2005: 921-926 |
144 | ![]() ![]() ![]() ![]() ![]() ![]() | Jie S. Hu, Feihui Li, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Compiler-Directed Instruction Duplication for Soft Error Detection. DATE 2005: 1056-1057 |
143 | ![]() ![]() ![]() ![]() ![]() ![]() | Suresh Srinivasan, Lin Li, Narayanan Vijaykrishnan: Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures. DATE 2005: 218-223 |
142 | ![]() ![]() ![]() ![]() ![]() ![]() | Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Leakage-Aware Interconnect for On-Chip Network. DATE 2005: 230-231 |
141 | ![]() ![]() ![]() ![]() ![]() ![]() | Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan, Dimitrios N. Serpanos, Yuan Xie: Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach. DATE 2005: 64-69 |
140 | ![]() ![]() ![]() ![]() ![]() ![]() | Greg M. Link, Narayanan Vijaykrishnan: Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip. DATE 2005: 648-649 |
139 | ![]() ![]() ![]() ![]() ![]() ![]() | Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Thermal-Aware Task Allocation and Scheduling for Embedded Systems. DATE 2005: 898-899 |
138 | ![]() ![]() ![]() ![]() ![]() ![]() | E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan: Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only). FPGA 2005: 265 |
137 | ![]() ![]() ![]() ![]() ![]() ![]() | Yuh-Fang Tsai, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: Three-Dimensional Cache Design Exploration Using 3DCacti. ICCD 2005: 519-524 |
136 | ![]() ![]() ![]() ![]() ![]() ![]() | Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Nagu R. Dhanwada, John Conner: Temperature-Aware Voltage Islands Architecting in System-on-Chip Design. ICCD 2005: 689-696 |
135 | ![]() ![]() ![]() ![]() ![]() ![]() | E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan: Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs. IPDPS 2005 |
134 | ![]() ![]() ![]() ![]() ![]() ![]() | Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Charles Addo-Quaye, Theo Theocharides, Mary Jane Irwin: Thermal-Aware Floorplanning Using Genetic Algorithms. ISQED 2005: 634-639 |
133 | ![]() ![]() ![]() ![]() ![]() ![]() | Hendra Saputra, Ozcan Ozturk, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Richard R. Brooks: A Data-Driven Approach for Embedded Security. ISVLSI 2005: 104-109 |
132 | ![]() ![]() ![]() ![]() ![]() ![]() | J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin: High Performance Array Processor for Video Decoding. ISVLSI 2005: 28-33 |
131 | ![]() ![]() ![]() ![]() ![]() ![]() | Theo Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin: Implementing LDPC Decoding on Network-on-Chip. VLSI Design 2005: 134-137 |
130 | ![]() ![]() ![]() ![]() ![]() ![]() | Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan, Yuan Xie, Wenping Wang: Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits. VLSI Design 2005: 165-170 |
129 | ![]() ![]() ![]() ![]() ![]() ![]() | Kevin M. Irick, Wei Xu, Narayanan Vijaykrishnan, Mary Jane Irwin: A Nanosensor Array-Based VLSI Gas Discriminator. VLSI Design 2005: 241-246 |
128 | ![]() ![]() ![]() ![]() ![]() ![]() | Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty. VLSI Design 2005: 374-379 |
127 | ![]() ![]() ![]() ![]() ![]() ![]() | E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan: Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs. VLSI Design 2005: 736-741 |
126 | ![]() ![]() ![]() ![]() ![]() ![]() | Ismail Kadayif, Mahmut T. Kandemir, Guilin Chen, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam: Compiler-directed high-level energy estimation and optimization. ACM Trans. Embedded Comput. Syst. 4(4): 819-850 (2005) |
125 | ![]() ![]() ![]() ![]() ![]() ![]() | J. Hu, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Analyzing data reuse for cache reconfiguration. ACM Trans. Embedded Comput. Syst. 4(4): 851-876 (2005) |
124 | ![]() ![]() ![]() ![]() ![]() ![]() | Theocharis Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin: Networks on Chip (NoC): Interconnects of Next Generation Systems on Chip. Advances in Computers 63: 36-92 (2005) |
123 | ![]() ![]() ![]() ![]() ![]() ![]() | Srinivasan Murali, Theo Theocharides, Narayanan Vijaykrishnan, Mary Jane Irwin, Luca Benini, Giovanni De Micheli: Analysis of Error Recovery Schemes for Networks on Chips. IEEE Design & Test of Computers 22(5): 434-442 (2005) |
122 | ![]() ![]() ![]() ![]() ![]() ![]() | Eun Jung Kim, Greg M. Link, Ki Hwan Yum, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Chita R. Das: A Holistic Approach to Designing Energy-Efficient Cluster Interconnects. IEEE Trans. Computers 54(6): 660-671 (2005) |
121 | ![]() ![]() ![]() ![]() ![]() ![]() | Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan: Power and Performance Analysis of Motion Estimation Based on Hardware and Software Realizations. IEEE Trans. Computers 54(6): 714-726 (2005) |
120 | ![]() ![]() ![]() ![]() ![]() ![]() | Vijay Degalahal, Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Soft errors issues in low-power caches. IEEE Trans. VLSI Syst. 13(10): 1157-1166 (2005) |
119 | ![]() ![]() ![]() ![]() ![]() ![]() | Eric J. Swankoski, Narayanan Vijaykrishnan, Richard R. Brooks, Mahmut T. Kandemir, Mary Jane Irwin: Symmetric encryption in reconfigurable and custom hardware. IJES 1(3/4): 205-217 (2005) |
118 | ![]() ![]() ![]() ![]() ![]() ![]() | Emanuele Lattanzi, Aman Gayasen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Luca Benini, Alessandro Bogliolo: Improving Java performance using dynamic method migration on FPGAs. IJES 1(3/4): 228-236 (2005) |
117 | ![]() ![]() ![]() ![]() ![]() ![]() | Ismail Kadayif, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: An integer linear programming-based tool for wireless sensor networks. J. Parallel Distrib. Comput. 65(3): 247-260 (2005) |
116 | ![]() ![]() ![]() ![]() ![]() ![]() | Mary Jane Irwin, Narayanan Vijaykrishnan: Editorial. JETC 1(1): 1-6 (2005) |
2004 | ||
115 | ![]() ![]() ![]() ![]() ![]() ![]() | Wei Xu, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Design of a nanosensor array architecture. ACM Great Lakes Symposium on VLSI 2004: 298-303 |
114 | ![]() ![]() ![]() ![]() ![]() ![]() | Yuan Xie, Lin Li, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Reliability-Aware Co-Synthesis for Embedded Systems. ASAP 2004: 41-50 |
113 | ![]() ![]() ![]() ![]() ![]() ![]() | Guilin Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin: Analyzing heap error behavior in embedded JVM environments. CODES+ISSS 2004: 230-235 |
112 | ![]() ![]() ![]() ![]() ![]() ![]() | Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: A Crosstalk Aware Interconnect with Variable Cycle Transmission. DATE 2004: 102-107 |
111 | ![]() ![]() ![]() ![]() ![]() ![]() | Jie S. Hu, Narayanan Vijaykrishnan, Soontae Kim, Mahmut T. Kandemir, Mary Jane Irwin: Scheduling Reusable Instructions for Power Reduction. DATE 2004: 148-155 |
110 | ![]() ![]() ![]() ![]() ![]() ![]() | Aman Gayasen, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan: Reducing leakage energy in FPGAs using region-constrained placement. FPGA 2004: 51-58 |
109 | ![]() ![]() ![]() ![]() ![]() ![]() | Aman Gayasen, K. Lee, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan: A Dual-VDD Low Power FPGA Architecture. FPL 2004: 145-157 |
108 | ![]() ![]() ![]() ![]() ![]() ![]() | Jie S. Hu, Narayanan Vijaykrishnan, Mary Jane Irwin: Exploring Wakeup-Free Instruction Scheduling. HPCA 2004: 232-243 |
107 | ![]() ![]() ![]() ![]() ![]() ![]() | Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Yuan Xie, Mary Jane Irwin: Improving soft-error tolerance of FPGA configuration bits. ICCAD 2004: 107-110 |
106 | ![]() ![]() ![]() ![]() ![]() ![]() | Frank Ghenassia, Narayanan Vijaykrishnan, Mary Jane Irwin: Analyzing software influences on substrate noise: an ADC perspective. ICCAD 2004: 916-922 |
105 | ![]() ![]() ![]() ![]() ![]() ![]() | Wei-Lun Hung, Charles Addo-Quaye, Theo Theocharides, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture. ICCD 2004: 430-437 |
104 | ![]() ![]() ![]() ![]() ![]() ![]() | Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan: Search speed and power driven integrated software and hardware optimizations for motion estimation algorithms. ICME 2004: 707-710 |
103 | ![]() ![]() ![]() ![]() ![]() ![]() | Eric J. Swankoski, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: A Parallel Architecture for Secure FPGA Symmetric Encryption. IPDPS 2004 |
102 | ![]() ![]() ![]() ![]() ![]() ![]() | Emanuele Lattanzi, Aman Gayasen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Luca Benini, Alessandro Bogliolo: Improving Java Performance Using Dynamic Method Migration on FPGAs. IPDPS 2004 |
101 | ![]() ![]() ![]() ![]() ![]() ![]() | Lin Li, Vijay Degalahal, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Soft error and energy consumption interactions: a data cache perspective. ISLPED 2004: 132-137 |
100 | ![]() ![]() ![]() ![]() ![]() ![]() | Guangyu Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Field level analysis for heap space optimization in embedded java environments. ISMM 2004: 131-142 |
99 | ![]() ![]() ![]() ![]() ![]() ![]() | Vijay Degalahal, Rajaraman Ramanarayanan, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: The Effect of Threshold Voltages on the Soft Error Rate. ISQED 2004: 503-508 |
98 | ![]() ![]() ![]() ![]() ![]() ![]() | Matthew Pirretti, Greg M. Link, Richard R. Brooks, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Fault Tolerant Algorithms for Network-On-Chip Interconnect. ISVLSI 2004: 46-51 |
97 | ![]() ![]() ![]() ![]() ![]() ![]() | Theo Theocharides, Greg M. Link, Eric J. Swankoski, Narayanan Vijaykrishnan, Mary Jane Irwin, Herman Schmit: Evaluating Alternative Implementations for LDPC Decoder Check Node Function. ISVLSI 2004: 77-82 |
96 | ![]() ![]() ![]() ![]() ![]() ![]() | Hendra Saputra, Guangyu Chen, Richard R. Brooks, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Code protection for resource-constrained embedded devices. LCTES 2004: 240-248 |
95 | ![]() ![]() ![]() ![]() ![]() ![]() | J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne Wolf: An Architecture for Motion Estimation in the Transform Domain. VLSI Design 2004: 1077-1082 |
94 | ![]() ![]() ![]() ![]() ![]() ![]() | Theo Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne Wolf: Embedded Hardware Face Detection. VLSI Design 2004: 133- |
93 | ![]() ![]() ![]() ![]() ![]() ![]() | M. DeRenzo, Mary Jane Irwin, Narayanan Vijaykrishnan: Designing Leakage Aware Multipliers. VLSI Design 2004: 654-657 |
92 | ![]() ![]() ![]() ![]() ![]() ![]() | Guangyu Chen, Byung-Tae Kang, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Rajarathnam Chandramouli: Studying Energy Trade Offs in Offloading Computation/Compilation in Java-Enabled Mobile Devices. IEEE Trans. Parallel Distrib. Syst. 15(9): 795-809 (2004) |
91 | ![]() ![]() ![]() ![]() ![]() ![]() | Yuh-Fang Tsai, D. E. Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin: Characterization and modeling of run-time techniques for leakage power reduction. IEEE Trans. VLSI Syst. 12(11): 1221-1233 (2004) |
90 | ![]() ![]() ![]() ![]() ![]() ![]() | Christian Piguet, Narayanan Vijaykrishnan: Guest Editorial. IEEE Trans. VLSI Syst. 12(2): 129-130 (2004) |
89 | ![]() ![]() ![]() ![]() ![]() ![]() | Christian Piguet, Narayanan Vijaykrishnan: Guest Editorial. IEEE Trans. VLSI Syst. 12(3): 233-234 (2004) |
88 | ![]() ![]() ![]() ![]() ![]() ![]() | Mahmut T. Kandemir, J. Ramanujam, Mary Jane Irwin, Narayanan Vijaykrishnan, Ismail Kadayif, Amisha Parikh: A compiler-based approach for dynamically managing scratch-pad memories in embedded systems. IEEE Trans. on CAD of Integrated Circuits and Systems 23(2): 243-260 (2004) |
87 | ![]() ![]() ![]() ![]() ![]() ![]() | Wei Zhang, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Reducing instruction cache energy consumption using a compiler-based strategy. TACO 1(1): 3-33 (2004) |
86 | ![]() ![]() ![]() ![]() ![]() ![]() | Amisha Parikh, Soontae Kim, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Instruction Scheduling for Low Power. VLSI Signal Processing 37(1): 129-149 (2004) |
85 | ![]() ![]() ![]() ![]() ![]() ![]() | J. Juran, Ali R. Hurson, Narayanan Vijaykrishnan, Soontae Kim: Data Organization and Retrieval on Parallel Air Channels: Performance and Energy Issues. Wireless Networks 10(2): 183-195 (2004) |
2003 | ||
84 | ![]() ![]() ![]() ![]() ![]() ![]() | Ananth Hegde, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: VL-CDRAM: variable line sized cached DRAMs. CODES+ISSS 2003: 132-137 |
83 | ![]() ![]() ![]() ![]() ![]() ![]() | Guangyu Chen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Mario Wolczko: Tracking object life cycle for leakage energy optimization. CODES+ISSS 2003: 213-218 |
82 | ![]() ![]() ![]() ![]() ![]() ![]() | Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin: Implications of technology scaling on leakage reduction techniques. DAC 2003: 187-190 |
81 | ![]() ![]() ![]() ![]() ![]() ![]() | Hendra Saputra, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Richard R. Brooks, Soontae Kim, Wei Zhang: Masking the Energy Behavior of DES Encryption. DATE 2003: 10084-10089 |
80 | ![]() ![]() ![]() ![]() ![]() ![]() | Wei Zhang, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Vivek De: Compiler Support for Reducing Leakage Energy Consumption. DATE 2003: 11146-11147 |
79 | ![]() ![]() ![]() ![]() ![]() ![]() | Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Ismail Kadayif: CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors. DSD 2003: 41-49 |
78 | ![]() ![]() ![]() ![]() ![]() ![]() | Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Adapative Error Protection for Energy Efficiency. ICCAD 2003: 2-7 |
77 | ![]() ![]() ![]() ![]() ![]() ![]() | Victor Delaluz, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin, Narayanan Vijaykrishnan: Reducing dTLB Energy Through Dynamic Resizing. ICCD 2003: 358-363 |
76 | ![]() ![]() ![]() ![]() ![]() ![]() | Sudhanva Gurumurthi, Ning An, Anand Sivasubramaniam, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Energy and Performance Considerations in Work Partitioning for Mobile Spatial Queries. IPDPS 2003: 33 |
75 | ![]() ![]() ![]() ![]() ![]() ![]() | Guilin Chen, Byung-Tae Kang, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Rajarathnam Chandramouli: Energy-Aware Compilation and Execution in Java-Enabled Mobile Devices. IPDPS 2003: 34 |
74 | ![]() ![]() ![]() ![]() ![]() ![]() | Soontae Kim, Narayanan Vijaykrishnan, Mary Jane Irwin, Lizy Kurian John: On load latency in low-power caches. ISLPED 2003: 258-261 |
73 | ![]() ![]() ![]() ![]() ![]() ![]() | Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Erik Brockmeyer, Francky Catthoor, Mary Jane Irwin: Estimating influence of data layout optimizations on SDRAM energy consumption. ISLPED 2003: 40-43 |
72 | ![]() ![]() ![]() ![]() ![]() ![]() | Jie S. Hu, A. Nadgir, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir: Exploiting program hotspots and code sequentiality for instruction cache leakage management. ISLPED 2003: 402-407 |
71 | ![]() ![]() ![]() ![]() ![]() ![]() | Eun Jung Kim, Ki Hwan Yum, Greg M. Link, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Mazin S. Yousif, Chita R. Das: Energy optimization techniques in cluster interconnects. ISLPED 2003: 459-464 |
70 | ![]() ![]() ![]() ![]() ![]() ![]() | Sudhanva Gurumurthi, Jianyong Zhang, Anand Sivasubramaniam, Mahmut T. Kandemir, Hubertus Franke, Narayanan Vijaykrishnan, Mary Jane Irwin: Interplay of energy and performance for disk arrays running transaction processing workloads. ISPASS 2003: 123-132 |
69 | ![]() ![]() ![]() ![]() ![]() ![]() | Jie S. Hu, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir: Using Dynamic Branch Behavior for Power-Efficient Instruction Fetch. ISVLSI 2003: 127-132 |
68 | ![]() ![]() ![]() ![]() ![]() ![]() | Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Adapting instruction level parallelism for optimizing leakage in VLIW architectures. LCTES 2003: 275-283 |
67 | ![]() ![]() ![]() ![]() ![]() ![]() | Herman Schmit, Thomas Kroll, Max Khusid, Ivan S. Kourtev, Narayanan Vijaykrishnan, David L. Landis: The Sandbox Design Experience Course. MSE 2003: 39-40 |
66 | ![]() ![]() ![]() ![]() ![]() ![]() | Guangyu Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Bernd Mathiske, Mario Wolczko: Heap compression for memory-constrained Java environments. OOPSLA 2003: 282-301 |
65 | ![]() ![]() ![]() ![]() ![]() ![]() | Vijay Degalahal, Narayanan Vijaykrishnan, Mary Jane Irwin: Analyzing Soft Errors in Leakage Optimized SRAM Design. VLSI Design 2003: 227-233 |
64 | ![]() ![]() ![]() ![]() ![]() ![]() | Narayanan Vijaykrishnan: Energy Efficient and Reliable System Design. VLSI-SOC 2003: 6-9 |
63 | ![]() ![]() ![]() ![]() ![]() ![]() | Soontae Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin: Partitioned instruction cache architecture for energy efficiency. ACM Trans. Embedded Comput. Syst. 2(2): 163-185 (2003) |
62 | ![]() ![]() ![]() ![]() ![]() ![]() | Nam Sung Kim, Todd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner, Jie S. Hu, Mary Jane Irwin, Mahmut T. Kandemir, Narayanan Vijaykrishnan: Leakage Current: Moore's Law Meets Static Power. IEEE Computer 36(12): 68-75 (2003) |
61 | ![]() ![]() ![]() ![]() ![]() ![]() | Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Hyun Suk Kim, Wu Ye, David Duarte: Evaluating Integrated Hardware-Software Optimizations Using a Unified Energy Estimation Framework. IEEE Trans. Computers 52(1): 59-76 (2003) |
60 | ![]() ![]() ![]() ![]() ![]() ![]() | Lin Li, Ismail Kadayif, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Anand Sivasubramaniam: Managing Leakage Energy in Cache Hierarchies. J. Instruction-Level Parallelism 5: (2003) |
2002 | ||
59 | ![]() ![]() ![]() ![]() ![]() ![]() | Tao Li, Lizy Kurian John, Anand Sivasubramaniam, Narayanan Vijaykrishnan, Juan Rubio: Understanding and improving operating system effects in control flow prediction. ASPLOS 2002: 68-80 |
58 | ![]() ![]() ![]() ![]() ![]() ![]() | Guangyu Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne Wolf: Energy savings through compression in embedded Java environments. CODES 2002: 163-168 |
57 | ![]() ![]() ![]() ![]() ![]() ![]() | Victor Delaluz, Anand Sivasubramaniam, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Scheduler-based DRAM energy management. DAC 2002: 697-702 |
56 | ![]() ![]() ![]() ![]() ![]() ![]() | Jie S. Hu, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Power-Efficient Trace Caches. DATE 2002: 1091 |
55 | ![]() ![]() ![]() ![]() ![]() ![]() | David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin: A Complete Phase-Locked Loop Power Consumption Model. DATE 2002: 1108 |
54 | ![]() ![]() ![]() ![]() ![]() ![]() | Ismail Kadayif, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam: EAC: A Compiler Framework for High-Level Energy Estimation and Optimization. DATE 2002: 436-442 |
53 | ![]() ![]() ![]() ![]() ![]() ![]() | Sudhanva Gurumurthi, Anand Sivasubramaniam, Mary Jane Irwin, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Tao Li, Lizy Kurian John: Using Complete Machine Simulation for Software Power Estimation: The SoftWatt Approach. HPCA 2002: 141-150 |
52 | ![]() ![]() ![]() ![]() ![]() ![]() | Guangyu Chen, R. Shetty, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Mario Wolczko: Tuning Garbage Collection in an Embedded Java Environment. HPCA 2002: 92- |
51 | ![]() ![]() ![]() ![]() ![]() ![]() | David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin, Hyun Suk Kim, G. McFarland: Impact of Scaling on the Effectiveness of Dynamic Power Reduction Schemes. ICCD 2002: 382-387 |
50 | ![]() ![]() ![]() ![]() ![]() ![]() | Lin Li, Ismail Kadayif, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Anand Sivasubramaniam: Leakage Energy Management in Cache Hierarchies. IEEE PACT 2002: 131-140 |
49 | ![]() ![]() ![]() ![]() ![]() ![]() | Anand Sivasubramaniam, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Designing Energy-Efficient Software. IPDPS 2002 |
48 | ![]() ![]() ![]() ![]() ![]() ![]() | Ismail Kadayif, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Hardware-Software Co-Adaptation for Data-Intensive Embedded Applications. ISVLSI 2002: 20-25 |
47 | ![]() ![]() ![]() ![]() ![]() ![]() | David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin: Impact of Technology Scaling in the Clock System Power. ISVLSI 2002: 59-64 |
46 | ![]() ![]() ![]() ![]() ![]() ![]() | Guangyu Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Mario Wolczko: Adaptive Garbage Collection for Battery-Operated Environments. Java Virtual Machine Research and Technology Symposium 2002: 1-12 |
45 | ![]() ![]() ![]() ![]() ![]() ![]() | Jie S. Hu, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Hendra Saputra, Wei Zhang: Compiler-directed cache polymorphism. LCTES-SCOPES 2002: 165-174 |
44 | ![]() ![]() ![]() ![]() ![]() ![]() | Hendra Saputra, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Jie S. Hu, Chung-Hsing Hsu, Ulrich Kremer: Energy-conscious compilation based on voltage scaling. LCTES-SCOPES 2002: 2-11 |
43 | ![]() ![]() ![]() ![]() ![]() ![]() | Wei Zhang, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Compiler-directed instruction cache leakage optimization. MICRO 2002: 208-218 |
42 | ![]() ![]() ![]() ![]() ![]() ![]() | Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam, Ibrahim Kolcu: Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories. VLSI Design 2002: 288- |
41 | ![]() ![]() ![]() ![]() ![]() ![]() | David Duarte, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mary Jane Irwin: Evaluating Run-Time Techniques for Leakage Power Reduction. VLSI Design 2002: 31-38 |
40 | ![]() ![]() ![]() ![]() ![]() ![]() | Guangyu Chen, R. Shetty, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Mario Wolczko: Tuning garbage collection for reducing memory system energy in an embedded java environment. ACM Trans. Embedded Comput. Syst. 1(1): 27-55 (2002) |
39 | ![]() ![]() ![]() ![]() ![]() ![]() | D. E. Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin: A clock power model to evaluate impact of architectural and technology optimizations. IEEE Trans. VLSI Syst. 10(6): 844-855 (2002) |
38 | ![]() ![]() ![]() ![]() ![]() ![]() | Guangyu Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne Wolf: Using Memory Compression for Energy Reduction in an Embedded Java System. Journal of Circuits, Systems, and Computers 11(5): 537-556 (2002) |
37 | ![]() ![]() ![]() ![]() ![]() ![]() | Ning An, Sudhanva Gurumurthi, Anand Sivasubramaniam, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Energy-performance trade-offs for spatial access methods on memory-resident data. VLDB J. 11(3): 179-197 (2002) |
2001 | ||
36 | ![]() ![]() ![]() ![]() ![]() ![]() | Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Energy-efficient instruction cache using page-based placement. CASES 2001: 229-237 |
35 | ![]() ![]() ![]() ![]() ![]() ![]() | Mahmut T. Kandemir, J. Ramanujam, Mary Jane Irwin, Narayanan Vijaykrishnan, Ismail Kadayif, Amisha Parikh: Dynamic Management of Scratch-Pad Memory Space. DAC 2001: 690-695 |
34 | ![]() ![]() ![]() ![]() ![]() ![]() | Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin: DRAM Energy Management Using Software and Hardware Directed Power Mode Control. HPCA 2001: 159-170 |
33 | ![]() ![]() ![]() ![]() ![]() ![]() | Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: A Framework for Energy Estimation of VLIW Architecture. ICCD 2001: 40-45 |
32 | ![]() ![]() ![]() ![]() ![]() ![]() | Samarjeet Singh Tomar, Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Use of Local Memory for Efficient Java Execution. ICCD 2001: 468-476 |
31 | ![]() ![]() ![]() ![]() ![]() ![]() | R. Athavale, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Influence of Array Allocation Mechanisms on Memory System Energy. IPDPS 2001: 3 |
30 | ![]() ![]() ![]() ![]() ![]() ![]() | Soontae Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin, E. Geethanjali: Power-aware partitioned cache architectures. ISLPED 2001: 64-67 |
29 | ![]() ![]() ![]() ![]() ![]() ![]() | Narayanan Vijaykrishnan, Mahmut T. Kandemir, Soontae Kim, Samarjeet Singh Tomar, Anand Sivasubramaniam, Mary Jane Irwin: Energy Behavior of Java Applications from the Memory Perspective. Java Virtual Machine Research and Technology Symposium 2001: 207-220 |
28 | ![]() ![]() ![]() ![]() ![]() ![]() | Ismail Kadayif, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, J. Ramanujam: Morphable Cache Architectures: Potential Benefits. LCTES/OM 2001: 128-137 |
27 | ![]() ![]() ![]() ![]() ![]() ![]() | Wei Zhang, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, David Duarte, Yuh-Fang Tsai: Exploiting VLIW schedule slacks for dynamic and leakage energy reduction. MICRO 2001: 102-113 |
26 | ![]() ![]() ![]() ![]() ![]() ![]() | Pradeep K. Khosla, Herman Schmit, Mary Jane Irwin, Narayanan Vijaykrishnan, Tom Cain, Steven P. Levitan, Dave Landis: SoC Design Skills: Collaboration Builds a Stronger SoC Design Team. MSE 2001: 42-43 |
25 | ![]() ![]() ![]() ![]() ![]() ![]() | Ismail Kadayif, T. Chinoda, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam: vEC: virtual energy counters. PASTE 2001: 28-31 |
24 | ![]() ![]() ![]() ![]() ![]() ![]() | Ning An, Anand Sivasubramaniam, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Sudhanva Gurumurthi: Analyzing energy behavior of spatial access methods for memory-resident data. VLDB 2001: 411-420 |
23 | ![]() ![]() ![]() ![]() ![]() ![]() | David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir: Formulation and Validation of an Energy Dissipation Model for the Clock Generation Circuitry and Distribution Networks. VLSI Design 2001: 248-253 |
22 | ![]() ![]() ![]() ![]() ![]() ![]() | Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin: Hardware and Software Techniques for Controlling DRAM Power Modes. IEEE Trans. Computers 50(11): 1154-1173 (2001) |
21 | ![]() ![]() ![]() ![]() ![]() ![]() | Ramesh Radhakrishnan, Narayanan Vijaykrishnan, Lizy Kurian John, Anand Sivasubramaniam, Juan Rubio, Jyotsna Sabarinathan: Java Runtime Systems: Characterization and Architectural Implications. IEEE Trans. Computers 50(2): 131-146 (2001) |
20 | ![]() ![]() ![]() ![]() ![]() ![]() | Benjamin Bishop, V. Lyuboslavsky, Narayanan Vijaykrishnan, Mary Jane Irwin: Design considerations for databus charge recovery. IEEE Trans. VLSI Syst. 9(1): 104-106 (2001) |
19 | ![]() ![]() ![]() ![]() ![]() ![]() | Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Wu Ye: Influence of compiler optimizations on system power. IEEE Trans. VLSI Syst. 9(6): 801-804 (2001) |
2000 | ||
18 | ![]() ![]() ![]() ![]() ![]() ![]() | Jeyran Hezavei, Narayanan Vijaykrishnan, Mary Jane Irwin: A comparative study of power efficient SRAM designs. ACM Great Lakes Symposium on VLSI 2000: 117-122 |
17 | ![]() ![]() ![]() ![]() ![]() ![]() | Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Energy-oriented compiler optimizations for partitioned memory architectures. CASES 2000: 138-147 |
16 | ![]() ![]() ![]() ![]() ![]() ![]() | Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Wu Ye: Influence of compiler optimizations on system power. DAC 2000: 304-307 |
15 | ![]() ![]() ![]() ![]() ![]() ![]() | Wu Ye, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: The design and use of simplepower: a cycle-accurate energy estimation tool. DAC 2000: 340-345 |
14 | ![]() ![]() ![]() ![]() ![]() ![]() | Ramesh Radhakrishnan, Narayanan Vijaykrishnan, Lizy Kurian John, Anand Sivasubramaniam: Architectural Issues in Java Runtime Systems. HPCA 2000: 387-398 |
13 | ![]() ![]() ![]() ![]() ![]() ![]() | Amisha Parikh, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Energy-Aware Instruction Scheduling. HiPC 2000: 335-344 |
12 | ![]() ![]() ![]() ![]() ![]() ![]() | J. Juran, Ali R. Hurson, Narayanan Vijaykrishnan, S. Boonsiriwattanakul: Data Organization and Retrieval on Parallel Air Channels. HiPC 2000: 501-510 |
11 | ![]() ![]() ![]() ![]() ![]() ![]() | Tao Li, Lizy Kurian John, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Jyotsna Sabarinathan, Anupama Murthy: Using complete system simulation to characterize SPECjvm98 benchmarks. ICS 2000: 22-33 |
10 | ![]() ![]() ![]() ![]() ![]() ![]() | Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Hyun Suk Kim, Wu Ye: Energy-driven integrated hardware-software optimizations using SimplePower. ISCA 2000: 95-106 |
9 | ![]() ![]() ![]() ![]() ![]() ![]() | G. Esakkimuthu, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Memory system energy (poster session): influence of hardware-software optimizations. ISLPED 2000: 244-246 |
8 | ![]() ![]() ![]() ![]() ![]() ![]() | Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Hyun Suk Kim: Experimental Evaluation of Energy Behavior of Iteration Space Tiling. LCPC 2000: 142-157 |
7 | ![]() ![]() ![]() ![]() ![]() ![]() | Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Hyun Suk Kim: Towards Energy-Aware Iteration Space Tiling. LCTES 2000: 211-215 |
6 | ![]() ![]() ![]() ![]() ![]() ![]() | Mary Jane Irwin, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam: A Holistic Approach to System Level Energy Optimization. PATMOS 2000: 88-107 |
1999 | ||
5 | ![]() ![]() ![]() ![]() ![]() ![]() | Narayanan Vijaykrishnan, N. Ranganathan: Tuning Branch Predictors to Support Virtual Method Invocation in Java. COOTS 1999: 217-228 |
4 | ![]() ![]() ![]() ![]() ![]() ![]() | Vamsi Krishna, N. Ranganathan, Narayanan Vijaykrishnan: Energy Efficient Datapath Synthesis Using Dynamic Frequency Clocking and Multiple Voltages. VLSI Design 1999: 440- |
1998 | ||
3 | ![]() ![]() ![]() ![]() ![]() ![]() | Narayanan Vijaykrishnan, N. Ranganathan, Ravi Gadekarla: Object-Oriented Architectural Support for a Java Processor. ECOOP 1998: 330-354 |
1996 | ||
2 | ![]() ![]() ![]() ![]() ![]() ![]() | N. Ranganathan, Narayanan Vijaykrishnan, N. Bhavanishankar: A VLSI array architecture with dynamic frequency clocking. ICCD 1996: 137-140 |
1 | ![]() ![]() ![]() ![]() ![]() ![]() | Narayanan Vijaykrishnan, N. Ranganathan: SUBGEN: a genetic approach for subcircuit extraction. VLSI Design 1996: 343-345 |