ICCD 1996: Austin, Texas, USA

@proceedings{DBLP:conf/iccd/1996,
  title     = {1996 International Conference on Computer Design (ICCD '96),
               VLSI in Computers and Processors, October 7-9, 1996, Austin,
               TX, USA, Proceedings},
  publisher = {IEEE Computer Society},
  year      = {1996},
  isbn      = {0-8186-7554-3},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

Verification

• Gianpiero Cabodi, Luciano Lavagno, Enrico Macii, Massimo Poncino, Stefano Quer, Paolo Camurati, Ellen Sentovich:
  Enhancing FSM Traversal by Temporary Re-Encoding. 6-11
  
• Ramin Hojati, Sriram C. Krishnan, Robert K. Brayton:
  Early Quantification and Partitioned Transition Relations. 12-19
  
• Michel Langevin, Sofiène Tahar, Zijian Zhou, Xiaoyu Song, Eduard Cerny:
  Behavioral Verification of an ATM Switch Fabric using Implicit Abstract State Enumeration. 20-26
  
• Valeria Bertacco, Maurizio Damiani:
  Boolean Function Representation Based on Disjoint-Support Decompositions. 27-
  

Design for Test

• Dimitrios Kagaris, Spyros Tragoudas:
  A multiseed counter TPG with performance guarantee. 34-39
  
• Karim Arabi, Bozena Kaminska, Stephen K. Sunter:
  Design for testability of integrated operational amplifiers using oscillation-test strategy. 40-45
  
• Kamran Zarrineh, Vivek Chickermane, Gareth Nicholls, Mike Palmer:
  A Design For Test Perspective on I/O Management. 46-
  

Opportunities and Pitfalls in HDL-Based System Design

• Rajesh K. Gupta, Daniel Gajski, Randy Allen, Yatin Trivedi:
  Opportunities and pitfalls in HDL-based system design. 56-
  

Issues on the Architecture and the Design of Distributed Shared Memory Systems

• Nian-Feng Tzeng, Steven Wallach:
  Issues on the architecture and the design of distributed shared memory systems. 60-61
  
• Daniel Lenoski:
  Design issues for distributed shared-memory systems. 62-62
  
• David A. Wood, Mark D. Hill, James R. Larus:
  The Tempest approach to distributed shared memory. 63-
  

Novel Aspects of Scheduling

• Pradeep Prabhakaran, Prithviraj Banerjee:
  Parallel Algorithms for Force Directed Scheduling of Flattened and Hierarchical Signal Flow Graphs. 66-71
  
• Mark C. Johnson, Kaushik Roy:
  Optimal Selection of Supply Voltages and Level Conversions During Data Path Scheduling Under Resource Constraints. 72-77
  
• Yung-Ming Fang, D. F. Wong:
  Multiplexor Network Generation in High Level Synthesis. 78-
  

Multimedia Systems

• William O'Connell, Grace Au, David Schrader:
  Multimodal query support in database servers. 86-92
  
• W. Melody Moh, Yu-Feng Chung, Teng-Sheng Moh, Joanna Wang:
  Evaluation of high speed LAN protocols as multimedia carriers . 93-
  
• David C. Chen, Bing J. Sheu, Theodore W. Berger:
  A Compact Neural Network Based CDMA Receiver for Multimedia Wireless Communication. 99-
  

System Design Aspect

• Yinan N. Shen, Nohpill Park, Fabrizio Lombardi:
  Space Cutting Approaches for Repairing Memories. 106-111
  
• Alex Orailoglu:
  Microarchitectural synthesis of gracefully degradable, dynamically reconfigurable ASICs. 112-117
  
• Kenneth Y. Yun, Ryan P. Donohue:
  Pausible Clocking: A First Step Toward Heterogeneous Systems. 118-
  

Processor Design Verification

• Peter Walker, Sumit Ghosh:
  On the Nature and Inadequacies of Transport Timing Delay Constructs in VHDL Descriptions. 128-130
  
• Albrecht P. Stroele:
  Arithmetic Pattern Generators for Built-In Self-Test. 131-134
  
• Naim Ben Hamida, Bechir Ayari, Bozena Kaminska:
  Testing of embedded A/D converters in mixed-signal circuit. 135-136
  
• N. Ranganathan, Narayanan Vijaykrishnan, N. Bhavanishankar:
  A VLSI array architecture with dynamic frequency clocking. 137-140
  
• Leon Alkalai, Wai-Chi Fang:
  An integrated microspacecraft avionics architecture using 3D multichip module building blocks. 141-144
  
• Michael Kozuch, Wayne Wolf, Andrew Wolfe:
  New Challenges for Video Servers: Performance of Non-Linear Applications under User Choice. 145-146
  
• Jin Li:
  An output-shared buffer ATM switch. 147-148
  
• Chie Dou, Ming-Der Shieh:
  A CAM-Based VLSI Architecture for Shared Buffer ATM Switch with Fuzzy Controlled Buffer Management. 149-
  

Design and Test Plenary

• Irith Pomeranz, Sudhakar M. Reddy:
  Fault Location based on Circuit Partitioning. 154-
  

Data Communication

• Alex Maniatopoulos, Theodore Antonakopoulos, Vassilios Makios:
  Design and Implementation of a new Synchronization Method for High-Speed Cell-based Network Interfaces. 158-164
  
• José Cruz-Rivera, D. Scott Wills, Thomas K. Gaylord, Elias N. Glytsis:
  Modeling the Technology Impact on the Design of a Two-Level Multicomputer Interconnection Network. 165-169
  
• Dimitrios N. Serpanos, Leonidas Georgiadis, T. Bouloutas:
  MMPacking: A Load and Storage Balancing Algorithm for Distributed Multimedia Servers. 170-
  

Design Automation for Embedded Systems

• Steve Fu:
  Memory Hierarchy Synthesis of a Multimedia Embedded Processor. 176-184
  
• Dirk Herrmann:
  High Speed Video Board as a Case Study for Hardware-Software Co-Design. 185-190
  
• Jean-Paul Theis, Lothar Thiele:
  VLIW-Processors under Periodic Real Time Constraints. 191-
  
• C. Alba, Luigi Carro, A. Lima, Altamiro Amadeu Susin:
  Embedded Systems Design with Frontend Compilers. 200-
  

Branch Predictio

• Mamoru Sakamoto, Toyohiko Yoshida, Yasuhiro Nunomura, Yukihiko Shimazu:
  Microarchitecture Support for Reducing Branch Penalty in a Supercscaler Processor. 208-216
  
• Pradeep K. Dubey, Ravi Nair:
  Profile-Driven Generation of Trace Samples. 217-224
  
• Yue Liu, David R. Kaeli:
  Branch-Directed and Stride-Based Data Cache Prefetching. 225-230
  
• Gyungho Lee, Bland Quattlebaum, Sangyeun Cho, Larry L. Kinney:
  Global Bus Design of a Bus-Based COMA Multiprocessor DICE. 231-
  

Automatic Test Pattern Generation

• Irith Pomeranz, Sudhakar M. Reddy:
  Fault Location Based on Circuit Partitioning. 242-247
  
• Li-C. Wang, M. Ray Mercer, Thomas W. Williams:
  A Better ATPG Algorithm and Its Design Principles. 248-253
  
• Jaehong Park, M. Ray Mercer:
  Using Functional Information and Strategy Switching in Sequential ATPG. 254-260
  
• Thomas E. Marchok, Wojciech Maly:
  Modeling the Difficulty of Sequential Automatic Test Pattern Generation. 261-
  

VLSI Layou

• Steven P. Larcombe, David J. Prendergast, Neil A. Thacker, Peter A. Ivey:
  Using Genetic Algorithms to Automate System Implementation in a Novel Three-Dimensional Packaging Technolog. 274-279
  
• J. Kampe, C. Wisser, G. Scarbata:
  Module Generators for a Regular Analog Layout. 280-292
  
• Jose Alvarez, Hector Sanchez, Roger Countryman, Mike Alexander, Carmine Nicoletta, Gianfranco Gerosa:
  A Scalable Resistor-less PLL Design for PowerPCTM Microprocessors. 293-300
  
• Mauricio Breternitz Jr., A. Manikonda, M. Ommerman, W. Su, A. Thornto:
  Design Tradeoffs and Experience with Motorola PowerPC? Migration Tool. 301-
  

Embedded Systems Tutorial

• Philip Koopman:
  Embedded System Design Issues (The Rest of the Story). 310-
  

VLSI Technology and Design

• Soo-Young Oh, Khalid Rahmat, O. Sam Nakagawa, J. Moll:
  A Scaling Scheme and Optimization Methodology for Deep Sub-Micron Interconnect. 320-325
  
• Fran Hancheck, Shantanu Dutt:
  Design Methodologies for Tolerating Cell and Interconnect Faults in FPGAs. 326-331
  
• Gin Yee, Carl Sechen:
  Clock-Delayed Domino for Adder and Combinational Logic Desig. 332-
  

Special Session

• Richard J. Lipton:
  DNA computations can have global memory. 344-
  

Architecture Plenar

• Olivier Thiry, Luc J. M. Claesen:
  A formal verification technique for embedded software. 352-357
  
• Rajeev K. Ranjan, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
  Binary decision diagrams on network of workstation. 358-364
  
• Prakash Arunachalam, Craig M. Chase, Dinos Moundanos:
  Distributed Binary Decision Diagrams for Verification of Large Circuit. 365-370
  
• Florian Krohm, Andreas Kuehlmann, Arjen Mets:
  The use of random simulation in formal verification. 371-
  

Minimization Techniques

• Bingzhong Guan, Carl Sechen:
  Large Standard Cell Libraries and Their Impact on Layout Area and Circuit Performanc. 378-383
  
• Roberto Bevacqua, Luca Guerrazzi, Fabrizio Ferrandi, Franco Fummi:
  Implicit Test Sequences Compaction for Decreasing Test Application Cos. 384-382
  
• Lakshmikant Bhupathi, Liang-Fang Chao:
  Dichotomy-based Model for FSM Power Minimization. 390-395
  
• Rajesh Pendurkar, Abhijit Chatterjee, Craig A. Tovey:
  Optimal single probe traversal algorithm for testing of MCM substrat. 396-
  

Future Asynchronous Designs

• Stas Polonsky:
  RSFQ: What We Know and What We Don't. 406-412
  
• Priyadarsan Patra, Donald S. Fussell:
  Efficient Delay-Insensitive RSFQ Circuits. 413-418
  
• Yoshio Kameda:
  Pulse-Driven Delay-Insensitive Circuits using Single-Flux-Quantum Devices. 419-425
  

Sequential Synthesis

• Olivier Coudert, C.-J. Richard Shi:
  Exact Dichotomy-based Constrained Encodi. 426-431
  
• Shaz Qadeer, Robert K. Brayton, Vigyan Singhal:
  Latch Redundancy Removal Without Global Reset. 432-439
  
• Naresh Maheshwari, Sachin S. Sapatnekar:
  A Practical Algorithm for Retiming Level-Clocked Circuits. 440-
  

Integration Support

• Luca Benini, Alessandro Bogliolo, Giovanni De Micheli:
  Distributed EDA Tool Integration: The PPP Paradigm. 448-453
  
• Bogdan G. Arsintescu:
  A Method for Analog Circuits Visualization. 454-459
  
• Kei-Yong Khoo, Alan N. Willson Jr.:
  Cycle-Based Timing Simulations Using Event-Stream. 460-
  

Performance Analysis and Validation

• Thomas M. Conte, Mary Ann Hirsch, Kishore N. Menezes:
  Reducing State Loss For Effective Trace Sampling of Superscalar Processors. 468-477
  
• Bryan Black, Andrew S. Huang, Mikko H. Lipasti, John Paul Shen:
  Can Trace-Driven Simulators Accurately Predict Superscalar Performance? 478-485
  
• Anthony-Trung Nguyen, Maged M. Michael, Arun Sharma, Josep Torrellas:
  The Augmint multiprocessor simulation toolkit for Intel x86 architectures. 486-490
  

VLSI Signal Processors

• Janardhan H. Satyanarayana, Keshab K. Parhi, Leilei Song, Yun-Nan Chang:
  Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers. 492-499
  
• S. B. Aruru, N. Ranganathan, Kameswara Rao Namuduri:
  A VLSI chip for image compression using variable block size segmentation. 500-505
  
• Chin-Long Wey: On Design of Efficient Square Generator. 506-

Architectural Issues in High Level Synthesis

• H. Fatih Ugurdag, Thomas E. Fuhrman:
  Autocircuit: a clock edge general behavioral synthesis system with a direct path to physical datapath. 514-529
  
• Nelson L. Passos, Edwin Hsing-Mean Sha:
  Synthesis of Multi-Dimensional Applications in VHDL. 530-
  

Arithmetic Circuits

• Yamin Li, Wanming Chu:
  A New Non-Restoring Square Root Algorithm and its VLSI Implementation. 538-544
  
• David R. Lutz, D. N. Jayasimha:
  Early Zero Detection. 545-
  

Synthesis for FPGAs

• D. Kuguris, Spyros Tragoudas:
  FPGA Module Minimization. 566-571
  
• Jason Cong, Chang Wu:
  An Improved Algorithm for Performance Optimal Technology Mapping with Retiming in LUT-Based FPGA Desig. 572-578
  
• Vijayanand Sankarasubramanian, Dinesh Bhatia:
  Multiway Partitioner for High Performance FPGA Based Board Architecture. 579-