IEEE Micro, Volume 23, 2003

Volume 23, Number 1, January/February 2003

• Pradip Bose:
  Looking Forward to Bright New Beginnings. 5-6
  

• Micro News 350-GHz transistor; New high-performance benchmarks. 6-7, 87
  

• John W. Lockwood:
  Guest Editor's Introduction: Hot Interconnects 10--Thinking beyond the Internet. 8-9
  
• François Abel, Cyriel Minkenberg, Ronald P. Luijten, Mitchell Gusat, Ilias Iliadis:
  10 A Four-Terabit Packet Switch Supporting Long Round-Trip Times. 10-24
  
• Hangsheng Wang, Li-Shiuan Peh, Sharad Malik:
  A Power Model for Routers: Modeling Alpha 21364 and InfiniBand Routers. 26-35
  
• Rong Pan, Balaji Prabhakar, Lee Breslau, Scott Shenker:
  Approximate Fair Allocation of Link Bandwidth. 36-43
  
• Rina Panigrahy, Samar Sharma:
  Sorting and Searching using Ternary CAMs. 44-53
  
• David V. Schuehler, John W. Lockwood:
  TCP Splitter: A TCP/IP Flow Monitor in Reconfigurable Hardware. 54-59
  
• Hans Eberle:
  A Radio Network for Monitoring and Diagnosing Computer Systems. 60-65
  

• Marc A. Viredaz, Deborah A. Wallach:
  Power Evaluation of a Handheld Computer. 66-74
  

• Richard H. Stern:
  Weird Turn of Events in Continuing Rambus Saga. 76-80
  

• Richard Mateosian:
  Leadership Annoyances. 82-83
  

• Shane M. Greenstein:
  Where Did the Internet Go? 84-86
  

Volume 23, Number 2, March/April 2003

• Pradip Bose:
  Issues and Trends in High-Performance Processor Cores. 5
  

• Micro News : Moving into the 90-nm chip market; PowerPC runs at up to 2.5 GHz. 6
  

• Richard Mateosian:
  Nuts and Bolts. 7, 77
  

• John Wawrzynek, Keith Diefendorff:
  Guest Editors' Introduction: Hot Chips 14 - Innovation in the Face of Uncertain Economics. 8-11
  
• Alfred K. Wong:
  Microlithography: Trends, Challenges, Solutions, and Their Impact on Design. 12-21
  
• Luiz André Barroso, Jeffrey Dean, Urs Hölzle:
  Web Search for a Planet: The Google Cluster Architecture. 22-28
  
• John Nickolls, L. J. Madar III, Scott Johnson, Viresh Rustagi, Ken Unger, Mustafiz Choudhury:
  Calisto: A Low-Power Single-Chip Multiprocessor Communications Platform. 29-43
  
• Cameron McNairy, Don Soltis:
  Itanium 2 Processor Microarchitecture. 44-55
  
• David Koufaty, Deborah T. Marr:
  Hyperthreading Technology in the Netburst Microarchitecture. 56-65
  
• Chetana N. Keltcher, Kevin J. McGrath, Ardsher Ahmed, Pat Conway:
  The AMD Opteron Processor for Multiprocessor Servers. 66-76
  

• Shane M. Greenstein:
  Too Much Internet Backbone? 78-80
  

Volume 23, Number 3, May/June 2003

• Pradip Bose:
  Design and Integration: Chip- and System-Level Challenges. 5
  

• Alberto L. Sangiovanni-Vincentelli, Luciano Lavagno:
  Guest Editors' Introduction: Trends and Directions in Microelectronics. 6-7
  
• Alberto L. Sangiovanni-Vincentelli:
  Electronic-System Design in the Automobile Industry. 8-18
  
• Theo A. C. M. Claasen:
  System on a Chip: Changing IC Design Today and in the Future. 20-26
  
• James D. Meindl:
  Interconnect Opportunities for Gigascale Integration. 28-35
  
• Bruno Murari:
  Integrating Nonelectronic Components into Electronic Microsystems. 36-44
  

• Nick Richardson, Lun Bin Huang, Razak Hossain, Julian Lewis, Tommy Zounes, Naresh Soni:
  The iCore 520-MHz Synthesizable CPU Core. 46-57
  
• Amaury Nève, Denis Flandre, Jean-Jacques Quisquater:
  SOI Technology for Future High-Performance Smart Cards. 58-67
  

• Shane M. Greenstein:
  An Era of Error. 68-69
  

• Richard Mateosian:
  Evolution. 70-72
  

Volume 23, Number 4, July/August 2003

• Pradip Bose:
  Editor-in-Chief?s Message: Adapting Old Paradigms to Meet New Challenges. 5
  

• News: Intel's earnings double in quarter; tiny bubbles key in future liquid-cooled systems; chip diet tests Cisco's resolve; Intel to release machine learning libraries; and proposal in to fit eight Alpha cores onto a chip. 6-7
  

• Shane M. Greenstein:
  Moore Meets Malthus in Multiples. 8-10
  

• Richard Mateosian:
  Managing Software Projects. 11-13
  

• Cristian Constantinescu:
  Trends and Challenges in VLSI Circuit Reliability. 14-19
  
• Stamatis Vassiliadis, Stephan Wong, Sorin Cotofana:
  Microcode Processing: Positioning and Directions. 21-31
  
• Wangyang Lai, Chin-Tau A. Lea:
  A Programmable State Machine Architecture for Packet Processing. 32-42
  
• Bruce L. Jacob:
  A Case for Studying DRAM Issues at the System Level. 44-56
  
• Kerem Karadayi, Vishal Markandey, Jeremiah Golston, Robert J. Gove, Yongmin Kim:
  Strategies for Mapping Algorithms to Mediaprocessors for High Performance. 58-70
  
• The Use and Abuse of SPEC: An ISCA Panel. 73-77
  

• Alan Clements:
  CSIDC: Competing Students Design Real-World Systems. 78-80
  

Volume 23, Number 5, September/October 2003

• Richard H. Stern:
  Unresolved Legal Questions about Patents and Standard Setting. 5, 72-74
  

• Richard Mateosian:
  So Many Books, So Little Time. 6-7, 79-80
  

• Pradip Bose, David H. Albonesi, Diana Marculescu:
  Guest Editors' Introduction: Power and Complexity Aware Design. 8-11
  
• Michael C. Huang, Daniel Chaver, Luis Piñuel, Manuel Prieto, Francisco Tirado:
  Customizing the Branch Predictor to Reduce Complexity and Energy Consumption. 12-25
  
• Lieven Eeckhout, Sébastien Nussbaum, James E. Smith, Koen De Bosschere:
  Statistical Simulation: Adding Efficiency to the Computer Designer's Toolbox. 26-38
  
• Nathalie Julien, Johann Laurent, Eric Senn, Eric Martin:
  Power Consumption Modeling and Characterization of the TI C6201. 40-49
  
• Jaume Abella, Ramon Canal, Antonio González:
  Power- and Complexity-Aware Issue Queue Designs. 50-58
  
• Joshua B. Fryman, Chad Huneycutt, Hsien-Hsin S. Lee, Kenneth M. Mackenzie, David E. Schimmel:
  Energy-Efficient Network Memory for Ubiquitous Devices. 60-70
  

• Shane M. Greenstein:
  Jumping on Bandwagons. 75-77
  

• Charles R. Moore:
  Managing the Transition from Complexity to Elegance: Knowing When You Have a Problem. 88, 86-87
  

Volume 23, Number 6, November/December 2003

• Letters. 5
  
• Charles R. Moore, Kevin W. Rudd, Ruby B. Lee, Pradip Bose:
  Guest Editors' Introduction: Micro's Top Picks from Microarchitecture Conferences. 8-10
  
• Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan:
  Checkpoint Processing and Recovery: An Efficient, Scalable Alternative to Reorder Buffers. 11-19
  
• Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt:
  Runahead Execution: An Effective Alternative to Large Instruction Windows. 20-25
  
• Michael K. Chen, Kunle Olukotun:
  The Jrpm System for Dynamically Parallelizing Sequential Java Programs. 26-35
  
• Christoforos E. Kozyrakis, David A. Patterson:
  Scalable Vector Processors for Embedded Systems. 36-45
  
• Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore:
  Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture. 46-51
  
• Kevin Skadron, Mircea R. Stan, Wei Huang, Sivakumar Velusamy, Karthik Sankaranarayanan, David Tarjan:
  Temperature-Aware Computer Systems: Opportunities and Challenges. 52-61
  
• Grigorios Magklis, Greg Semeraro, David H. Albonesi, Steve Dropsho, Sandhya Dwarkadas, Michael L. Scott:
  Dynamic Frequency and Voltage Scaling for a Multiple-Clock-Domain Microprocessor. 62-68
  
• Shubhendu S. Mukherjee, Christopher T. Weaver, Joel S. Emer, Steven K. Reinhardt, Todd M. Austin:
  Measuring Architectural Vulnerability Factors. 70-75
  
• Mohamed A. Gomaa, Chad Scarbrough, T. N. Vijaykumar, Irith Pomeranz:
  Transient-Fault Recovery for Chip Multiprocessors. 76-83
  
• Timothy Sherwood, Erez Perelman, Greg Hamerly, Suleyman Sair, Brad Calder:
  Discovering and Exploiting Program Phases. 84-93
  
• Alaa R. Alameldeen, David A. Wood:
  Addressing Workload Variability in Architectural Simulations. 94-98
  
• Changkyu Kim, Doug Burger, Stephen W. Keckler:
  Nonuniform Cache Architectures for Wire-Delay Dominated On-Chip Caches. 99-107
  
• Milo M. K. Martin, Mark D. Hill, David A. Wood:
  Token Coherence: A New Framework for Shared-Memory Multiprocessors. 108-116
  
• Ravi Rajwar, James A. Goodman:
  Transactional Execution: Toward Reliable, High-Performance Multithreading. 117-125
  
• José F. Martínez, Josep Torrellas:
  Speculative Synchronization: Programmability and Performance for Parallel Codes. 126-134